Semiconductor Memory Device

• US 20100144107A1
• Filed: 02/10/2010
• Published: 06/10/2010
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cummings, Steve, Tang, Sanh Dang, Haller, Gordon
• Granted Patent: US 8,222,105 B2
• Time in Patent Office: Days
• US Class Current: 438/253
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Claims

1-9. -9. (canceled)

10. A method of fabricating a memory device, the method comprising;

forming a semiconductor substrate having a first surface;

forming a recessed gate in the substrate, wherein the recessed gate defines a first and second lateral sides;

forming a first source/drain region on the first surface of the semiconductor substrate adjacent a first lateral side of the recessed gate;

forming a second source/drain region on the first surface of the semiconductor substrate adjacent a second lateral side of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is recessed into the semiconductor substrate;

forming a charge storage device above the semiconductor substrate, wherein the charge storage device is electrically coupled to the first source/drain region; and

forming a conductive data line between the charge storage device and the first surface of the semiconductor substrate, wherein the conductive data line comprises a first portion that extends a first height above the first surface of the semiconductor substrate and a second portion that extends downward from the first portion to electrically and physically contact the second source/drain region, and wherein the first and second portions are formed of the same material.

24. The method of claim 10 comprising forming the first and second source/drain regions to have coplanar upper surfaces.

25. The method of claim 10 comprising forming the charge storage device to comprise a capacitor.

26. The method of claim 10 comprising forming the capacitor to comprise:

a storage node;

a dielectric substantially surrounding the storage node; and

a top cell plate substantially surrounding the dielectric.

27. The method of claim 10 comprising forming the same material to comprise polysilicon.

28. The method of claim 10 comprising forming the same material to comprise silicide.

29. The method of claim 10 comprising forming the same material to comprise polysilicon and silicide.

30. The method of claim 10 comprising forming an upper surface of the gate to be elevationally below upper surfaces of each of the first and second source/drain regions.

31. The method of claim 30 comprising forming the upper surface of the gate to be elevationally closer to a lower surface of the second source/drain than to the second source/drain upper surface.

32. The method of claim 10 comprising forming an upper surface of the gate to be elevationally closer to lower surfaces of each of the first and second source/drain than to the first surface.

33. The method of claim 10 comprising forming a gate dielectric in contact with the recessed gate and to extend along the first and second lateral sides, and forming the gate dielectric to have an uppermost surface which is co-planar with the upper surfaces of each of the first and second source/drain.

11-23. -23. (canceled)

34. A method of fabricating a memory device, the method comprising;

forming a semiconductor substrate having a first surface;

forming a recessed gate in the substrate, wherein the recessed gate defines first and second lateral sides;

forming a first source/drain region on the first surface of the semiconductor substrate adjacent a first lateral side of the recessed gate;

forming a second source/drain region on the first surface of the semiconductor substrate adjacent a second lateral side of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is recessed into the semiconductor substrate;

depositing dielectric material over the recessed gate and the second source/drain region;

forming a charge storage device above the semiconductor substrate, wherein the charge storage device is electrically coupled to the first source/drain region;

forming a contact hole through the dielectric material to expose the second source/drain region;

depositing conductive material into the contact hole and forming a conductive data line between the charge storage device and the first surface of the semiconductor substrate with the conductive material, wherein the conductive data line comprises a first portion that extends a first height above the first surface of the semiconductor substrate and a second portion that extends downward from the first portion to electrically and physically contact the second source/drain region, and wherein the first and second portions are formed of said conductive material deposited into the contact hole.

35. The method of claim 34 wherein the dielectric material comprises oxide.

36. The method of claim 34 wherein the dielectric material comprises silicon dioxide.

37. The method of claim 34 comprising forming the conductive material to comprise polysilicon.

38. The method of claim 34 comprising forming the conductive material to comprise silicide.

39. The method of claim 34 comprising forming the conductive material to comprise polysilicon and silicide.

40. The method of claim 34 comprising forming an upper surface of the gate to be elevationally below upper surfaces of each of the first and second source/drain regions.

41. The method of claim 40 comprising forming the upper surface of the gate to be elevationally closer to a lower surface of the second source/drain than to the second source/drain upper surface.

42. The method of claim 34 comprising forming an upper surface of the gate to be elevationally closer to lower surfaces of each of the first and second source/drain than to the first surface.

43. The method of claim 34 comprising forming a gate dielectric in contact with the recessed gate and to extend along the first and second lateral sides, and forming the gate dielectric to have an uppermost surface which is co-planar with the upper surfaces of each of the first and second source/drain.