METHOD FOR MANUFACTURE OF SEMICONDUCTOR DEVICE

• US 20100144148A1
• Filed: 11/05/2009
• Published: 06/10/2010
• Est. Priority Date: 11/07/2008
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nagai, Satoshi, Fukuhara, Kazuya
• Application Number:
  US12/613,213
• Publication Number:
  US 20100144148A1
• Time in Patent Office: Days
• US Class Current: 438/689
• CPC Class Codes: G03F 7/70608 Monitoring the unpatterned workpiece, e.g. measuring thickness, reflectivity or effects of immersion liquid on resist

Abstract

A semiconductor device manufacturing method includes designing a resist structure including a film having antireflection function for exposure light and a resist on the film to be formed on a substrate, designing an exposure condition of the resist obtained by exposing and developing the resist such that a resist pattern is finished as designed, obtaining criteria value for estimating influence of a resist pattern upon a dimension or shape of a device pattern, the resist pattern being obtained by exposing the resist under the designed exposure condition and developing the exposed resist, the device pattern being obtained by etching the resist structure using the resist pattern as a mask, determining whether the designed exposure condition is acceptable or not based on the criteria value, and redesigning the exposure condition of the resist without changing the designed resist structure when the designed exposure condition is determined not acceptable.

Claims

1. A method for manufacturing a semiconductor device comprising:

designing a resist structure to be formed on a substrate, the resist structure comprising a film having antireflection function for exposure light and a resist provide on the film;

designing an exposure condition of the resist such that a resist pattern is finished as designed, the resist pattern being obtained by exposing and developing the resist;

obtaining criteria value for estimating influence of a resist pattern upon a dimension or shape of a device pattern, the resist pattern being obtained by exposing the resist under the designed exposure condition and developing the exposed resist, the device pattern being obtained by etching the resist structure by using the resist pattern as a mask;

determining whether the designed exposure condition is acceptable or not based on the criteria value; and

redesigning the exposure condition of the resist without changing the designed resist structure when the designed exposure condition is determined not acceptable.

2. The method according to claim 1,

further comprising forming a resist pattern by exposing the resist under the designed exposure condition and etching the substrate by using the resist pattern as a mask when the designed exposure condition is determined acceptable.

3. The method according to claim 1,

further comprising determining whether the redesigned exposure condition is acceptable or not.

4. The method according to claim 3,

further comprising forming a resist pattern by exposing the resist under the redesigned exposure condition and etching the substrate using the resist pattern as a mask when the redesigned exposure condition is determined acceptable.

5. The method according to claim 1,

wherein the exposure condition includes a secondary light source shape of an exposure apparatus, polarization state of an exposure light and an aberration of a projector lens of an exposure apparatus,

the redesigning the exposure condition of the resist includes redesigning at least one of the secondary light source shape, the polarization state and the aberration.

6. The method according to claim 1,

wherein the criteria value is dimension relating to width of the resist pattern, sidewall angle of the resist pattern, reduction of the resist pattern, exposure latitude, focus latitude or light distribution of the exposure light on the resist.

7. The method according to claim 1,

wherein the dimension relating to the width of the resist pattern is dimension of narrowed part in a height direction of the resist pattern, bottom dimension of the resist pattern, dimension at a position of narrowed part of the resist pattern at a specific height of the resist pattern, or dimension at a position of narrowed part of the resist pattern having the smallest dimension in width.

8. The method according to claim 1,

wherein the dimension relating to the width of the resist pattern is obtained based on a resist pattern predicted by calculation.

9. The method according to claim 1,

wherein the dimension relating to the width of the resist pattern is obtained by measuring a resist pattern actually formed.

10. The method according to claim 1,

wherein the resist structure further comprises a protective film for preventing a surface of the resist from liquid.

11. The method according to claim 1,

wherein the redesigning the exposure condition of the resist includes exposing the resist by using an exposure apparatus configured to control a state of polarization of the exposure light in a case of redesigning at least the state of polarization of the exposure light.

12. The method according to claim 11,

wherein the exposure apparatus comprises a laser device which includes a laser light source configured to emit a laser light, a control unit provide inside the laser light source and configured to control a state of polarization of the laser light.

13. The method according to claim 12,

wherein the control unit comprises a polarizer.

14. The method according to claim 11,

wherein the exposure apparatus comprises a laser device which includes a laser light source configured to emit a laser light, a control unit provide outside the laser light source and configured to control a state of polarization of the laser light.

15. The method according to claim 14,

wherein the control unit comprises a phase plate.