Bus-handling

• US 20100146169A1
• Filed: 12/05/2008
• Published: 06/10/2010
• Est. Priority Date: 12/05/2008
• Status: Abandoned Application

• Current Assignee: Nuvoton Technology Corporation (Winbond Electronics Corporation)
• Original Assignee: Nuvoton Technology Corporation (Winbond Electronics Corporation)
• Inventors: Flachs, Victor
• Application Number:
  US12/315,769
• Publication Number:
  US 20100146169A1
• Time in Patent Office: Days
• US Class Current: 710/105
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is in the sleep state. The processor additionally includes a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state.

Claims

1. A processor, comprising:

a processing unit having an active state and a sleep state in which at least one of the sub-sections of the processing unit is inactive;

a communication port adapted to receive signals from external units over a bus, which is configured not to be fully operative in the sleep state; and

a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission had started while the port was in the sleep state.

2. A processor according to claim 1, wherein the bus monitoring unit is configured to provide a wakeup signal to the processing unit, responsive to identifying a transmission on the bus that is directed to the communication port.

3. A processor according to claim 2, wherein the bus monitoring unit is configured to provide the wakeup signal and to stall the bus, substantially concurrently.

4. A processor according to claim 2, wherein the bus monitoring unit is configured to provide the wakeup signal before stalling the bus.

5. A processor according to claim 1, wherein the bus monitoring unit comprises an asynchronous unit which is adapted to identify transmissions on the bus without use of a time signal.

6. A processor according to claim 1, wherein the bus monitoring unit comprises a synchronous unit which identifies transmissions on the bus using a time signal.

7. A processor according to claim 1, wherein the bus monitoring unit is configured to provide the communication port with an imitation of a beginning portion of a transmission from an external unit, before releasing the bus.

8. A method of handling transmissions, comprising:

identifying a transmission received over a bus, while a port intended to receive the transmission is in a sleep state;

moving the port into an operative state; and

stalling the bus responsive to receiving the transmission, until the port is in the operative state.

9. The method of claim 8, comprising notifying the port, when it is in the operative state, that a transmission began whilst the port was in the sleep state.

10. The method of claim 8, comprising providing locally an imitation of a beginning of the identified transmission to the port, after it moves into the operative state, before releasing the stalling of the bus.