ENDURANCE MANAGEMENT TECHNIQUE

• US 20100146187A1
• Filed: 12/05/2008
• Published: 06/10/2010
• Est. Priority Date: 12/05/2008
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Coulson, Richard L., Grimsrud, Knut S.
• Application Number:
  US12/329,079
• Publication Number:
  US 20100146187A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

According to embodiments of the present invention, endurance management techniques are disclosures. Adherence to endurance and data retention ratings are ensured by managing write accesses to a memory device.

Claims

1. A method comprising:

tracking a magnitude of write cycles accessing a memory;

throttling additional write accesses to the memory when the magnitude of write cycles approaches a total write threshold that changes with time, wherein the throttling produces a gradual decrease in write performance of the memory.

2. The method as recited in claim 1, wherein the total write threshold increases with time.

3. The method as recited in claim 1, wherein the write performance of the memory is controlled based on the magnitude of write cycles and an amount of time the memory is idle.

4. The method as recited in claim 1, further comprising preventing other write accesses to the memory if the magnitude of write cycles reaches the total write threshold.

5. The method as recited in claim 1, wherein the write accesses to the memory that are throttled are write accesses from a host.

6. The method as recited in claim 1, wherein the write accesses to the memory that are throttled are write accesses from memory management functionality.

7. The method as recited in claim 1, wherein the memory is an array of flash cells.

8. An apparatus comprising:

a memory array;

a host interface for receiving access requests to the memory array from a host;

memory management functionality that produces write access requests to the memory array; and

a controller for controlling accesses to the memory array from the host interface and the memory management functionality, the controller configured to;

track a magnitude of write cycles accessing the memory array; and

throttle additional write accesses to the memory array when the magnitude of write cycles approaches a total write threshold that changes with time, wherein throttling additional write accessing produces a gradual decrease in write performance of the memory array.

9. The apparatus as recited in claim 8, wherein the total write threshold increases with time.

10. The apparatus as recited in claim 8, the controller further configured to prevent other write accesses to the memory array if the magnitude of write cycles reaches the total write threshold.

11. The apparatus as recited in claim 8, wherein the write accesses to the memory array that are throttled are from the host interface.

12. The apparatus as recited in claim 8, wherein the write accesses to the memory array that are throttled are from the memory management functionality.

13. The apparatus as recited in claim 8, wherein the write performance of the memory array is controlled based on the magnitude of write cycles and an amount of time the memory array is idle.

14. A system comprising:

a memory array;

a host that generates access requests to the memory array, the host comprising a processor and one or more input/output interfaces;

memory management functionality that produces write access requests to the memory array; and

a controller for controlling accesses to the memory array from the host and the memory management functionality, the controller configured to;

track a magnitude of write cycles accessing the memory array; and

throttle additional write accesses to the memory array when the magnitude of write cycles approaches a total write threshold that changes with time, wherein throttling additional write accessing produces a gradual decrease in write performance of the memory array.

15. The system as recited in claim 14, wherein the total write threshold increases with time.

16. The system as recited in claim 14, the controller further configured to prevent other write accesses to the memory array if the magnitude of write cycles reaches the total write threshold.

17. The system as recited in claim 14, wherein the write accesses to the memory array that are throttled are from the host.

18. The system as recited in claim 14, wherein the write accesses to the memory array that are throttled are from the memory management functionality.

19. The system as recited in claim 14, wherein the write performance of the memory array is controlled based on the magnitude of write cycles and an amount of time the memory array is idle.