METHOD TO VERIFY AN IMPLEMENTED COHERENCY ALGORITHM OF A MULTI PROCESSOR ENVIRONMENT
First Claim
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1. Method to verify an implemented coherency algorithm of a multi processor environment on a single processor model characterized by the steps of:
- generating a reference model reflecting a private cache hierarchy of a single processor within a multi processor environment,stimulating the private cache hierarchy with simulated requests and/or cross invalidations from a core side and/or from a nest side,augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, set based on interface events, wherein multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before.
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Abstract
A method to verify an implemented coherency algorithm of a multi processor environment on a single processor model is described, comprising the steps of:
- generating a reference model reflecting a private cache hierarchy of a single processor within a multi processor environment,
- stimulating the private cache hierarchy with simulated requests and/or cross invalidations from a core side and/or from a nest side,
- augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, set based on interface events,
- wherein multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before.
Further a single processor model and a computer program product to execute said method are described.
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Citations
7 Claims
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1. Method to verify an implemented coherency algorithm of a multi processor environment on a single processor model characterized by the steps of:
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generating a reference model reflecting a private cache hierarchy of a single processor within a multi processor environment, stimulating the private cache hierarchy with simulated requests and/or cross invalidations from a core side and/or from a nest side, augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, set based on interface events, wherein multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before. - View Dependent Claims (2, 3, 4)
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- 5. Single processor model to perform a method of claim characterized by a reference model reflecting a private cache hierarchy of a single processor within a multi processor environment, said reference model keeping four time stamps, two construction dates and two expiration dates, for every cacheline that populates the private cache hierarchy of the processor, a random simulation driver simulating a core of the single processor, a simulation driver simulating a nest accommodating a plurality of processors within a multi processor environment, a global time counter that is incremented every simulation cycle and a core observed time unit.
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7. A computer program product stored on a computer usable medium, comprising computer readable program means for causing a computer to perform the method of claim, when said computer program product is executed on a computer.
Specification