Group III-V devices with delta-doped layer under channel region
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Abstract
A group III-V material device has a delta-doped region below a channel region. This may improve the performance of the device by reducing the distance between the gate and the channel region.
157 Citations
24 Claims
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1. (canceled)
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6. A device comprising:
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a lower barrier region comprising InAlAs; a delta doped region on top of the lower barrier region; a quantum well channel region comprising InGaAs on top of the delta doped region; a first upper barrier region comprising InAlAs on top of the the quantum well channel region; a gate electrode on top of the upper barrier region; and a second upper barrier region comprising InP between the first upper barrier region and the gate electrode. - View Dependent Claims (2, 3, 4, 5, 7, 8, 9, 21, 22)
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10. (canceled)
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11. (canceled)
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15. (canceled)
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16. (canceled)
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17. A semiconductor transistor comprising:
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a substrate; a quantum well channel region comprising a group III-V material on the substrate; a delta-doped region between the quantum well channel region and the substrate; a first upper barrier region above the quantum well channel region; a lower barrier region below the quantum well channel region; a spacer region between the delta-doped region and the quantum well channel region; a high-k gate dielectric region above first upper barrier region; a gate electrode comprising a metal above the high-k gate dielectric region; a source contact on a first side of the high-k gate dielectric region; a drain contact on a second side of the high-k gate dielectric region opposite to the first side; and a second upper barrier region between the first upper barrier region and the high-k gate dielectric region, the second upper barrier region comprising InP. - View Dependent Claims (12, 13, 14, 18, 19, 23)
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20. A transistor comprising:
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a substrate comprising silicon; a buffer layer on the substrate, the buffer layer comprising a graded InyAl1-yAs material, with the y increasing as the distance from the substrate increases; a lower barrier layer on the buffer layer, the lower barrier layer comprising an InyAl1-yAs material, where y is between 0.52 and 0.70; a delta-doped layer on the lower barrier layer, the delta-doped layer comprising an InyAl1-yAs material that is substantially the same as the InyAl1-yAs material of the lower barrier layer, plus a dopant; a quantum well channel layer on the delta-doped layer, the quantum well channel layer comprising an InxGa1-xAs material, where x is between 0.53 and 1.0; a first upper barrier layer on the quantum well channel layer, the first upper barrier layer consisting of substantially the same material as the lower barrier layer; a second upper barrier layer on the first upper barrier layer, the second upper barrier layer comprising InP; a high-k gate dielectric layer on the second upper barrier layer; a gate electrode on the high-k gate dielectric layer, the gate electrode comprising a metal; a source contact on a first side of the gate electrode, the source contact comprising InGaAs; and a drain contact on a second side of the gate electrode opposite the first side, the drain contact comprising InGaAs. - View Dependent Claims (24)
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Specification