INTEGRATED CIRCUIT STRUCTURE

• US 20100148168A1
• Filed: 06/30/2009
• Published: 06/17/2010
• Est. Priority Date: 12/12/2008
• Status: Abandoned Application

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Lai, Chih-Ming, Cheng, Chun-Cheng, Yeh, Yung-Hui
• Application Number:
  US12/494,304
• Publication Number:
  US 20100148168A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1233 with different thicknesses of the active layer in different devices
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/45 Ohmic electrodes

Abstract

An integrated circuit structure including a substrate, an insulating layer, a first transistor and a second transistor is provided. The insulating layer, the first transistor and the second transistor are disposed on the substrate. The first transistor includes a first gate, a first oxide semiconductor layer, a first source and a first drain. A portion of the first source and the first drain directly contacting the first oxide semiconductor layer is composed of a Ti-containing metal. The second transistor includes a second gate, a second oxide semiconductor layer, a second source and a second drain. A portion of the second source and the second drain directly contacting the second oxide semiconductor layer is composed of a none-Ti-containing metal. In addition, the first oxide semiconductor layer and the second oxide semiconductor layer may have different thickness or different carrier concentrations.

Claims

1. An integrated circuit structure, at least comprising:

a substrate;

an insulating layer, disposed on the substrate;

a first transistor, at least comprising;

a first gate, disposed on the substrate;

a first oxide semiconductor layer, the insulating layer being disposed between the first gate and the first oxide semiconductor layer, and an area of the first gate being partially overlapped to that of the first oxide semiconductor layer;

a first source, connected to the first oxide semiconductor layer;

a first drain, connected to the first oxide semiconductor layer, and the first source and the first drain being respectively located at two sides of the first gate, wherein a portion of the first source and the first drain directly contacting the first oxide semiconductor layer is composed of a titanium (Ti)-containing metal.

a second transistor, electrically connected to the first transistor, and comprising;

a second gate, disposed on the substrate;

a second oxide semiconductor layer, the insulating layer being disposed between the second gate and the second oxide semiconductor layer, and an area of the second gate being partially overlapped to that of the second oxide semiconductor layer;

a second source, connected to the second oxide semiconductor layer; and

a second drain, connected to the second oxide semiconductor layer, and the second source and the second drain being respectively located at two sides of the second gate, wherein a portion of the second source and the second drain directly contacting the second oxide semiconductor layer is composed of a none-Ti-containing metal.

2. The integrated circuit structure as claimed in claim 1, wherein a thickness of the first oxide semiconductor layer is different to that of the second oxide semiconductor layer.

3. The integrated circuit structure as claimed in claim 1, wherein a carrier concentration of the first oxide semiconductor layer is different to that of the second oxide semiconductor layer.

4. The integrated circuit structure as claimed in claim 1, wherein the first gate is located between the substrate and the insulating layer.

5. The integrated circuit structure as claimed in claim 4, wherein the second gate is located between the substrate and the insulating layer.

6. The integrated circuit structure as claimed in claim 1, wherein the first gate is located on a side of the insulating layer departing from the substrate, and the insulating layer is located between the substrate and the first gate.

7. The integrated circuit structure as claimed in claim 6, wherein the second gate is located on a side of the insulating layer departing from the substrate, and the insulating layer is located between the substrate and the second gate.

8. The integrated circuit structure as claimed in claim 1, wherein the Ti-containing metal comprises Ti or Ti alloy.

9. The integrated circuit structure as claimed in claim 1 further comprising a connecting metal connected between the first transistor and the second transistor.

10. The integrated circuit structure as claimed in claim 1, wherein a material of the first oxide semiconductor layer and the second oxide semiconductor layer comprises zinc oxide, indium gallium zinc oxide or indium zinc tin oxide.

11. The integrated circuit structure as claimed in claim 1, wherein the substrate is a flexible substrate.

12. The integrated circuit structure as claimed in claim 11, wherein a material of the flexible substrate comprises polyimide, polyethylene naphthalate (PEN) or polyethylene terephthalate (PET).

13. An integrated circuit structure, at least comprising:

a substrate;

a first insulating layer, disposed on the substrate;

a second insulating layer, disposed on the substrate, and the first insulating layer being located between the second insulating layer and the substrate;

a first transistor, at least comprising;

a first gate, disposed between the first insulating layer and the substrate;

a first oxide semiconductor layer, the first insulating layer being disposed between the first gate and the first oxide semiconductor layer, and an area of the first gate being partially overlapped to that of the first oxide semiconductor layer;

a first source, connected to the first oxide semiconductor layer;

a first drain, connected to the first oxide semiconductor layer, and the first source and the first drain being respectively located at two sides of the first gate;

a second transistor, electrically connected to the first transistor, and comprising;

a second gate, disposed on the second insulating layer at a side departing from the substrate;

a second oxide semiconductor layer, the second insulating layer being disposed between the second gate and the second oxide semiconductor layer, and an area of the second gate being partially overlapped to that of the second oxide semiconductor layer, wherein a thickness of the first oxide semiconductor layer is different to that of the second oxide semiconductor layer;

a second source, connected to the second oxide semiconductor layer; and

a second drain, connected to the second oxide semiconductor layer, and the second source and the second drain being respectively located at two sides of the second gate.

14. The integrated circuit structure as claimed in claim 13 further comprising a connecting metal connected between the first transistor and the second transistor.

15. The integrated circuit structure as claimed in claim 13, wherein a material of the first oxide semiconductor layer and the second oxide semiconductor layer comprises zinc oxide, indium gallium zinc oxide or indium zinc tin oxide.

16. The integrated circuit structure as claimed in claim 13, wherein the substrate is a flexible substrate.

17. The integrated circuit structure as claimed in claim 16, wherein a material of the flexible substrate comprises polyimide, PEN or PET.

18. The integrated circuit structure as claimed in claim 13, wherein a thickness of the first oxide semiconductor layer is greater than 50 nm, and a thickness of the second oxide semiconductor layer is less than 50 nm.

19. The integrated circuit structure as claimed in claim 13, wherein a thickness of the first oxide semiconductor layer is less than 50 nm, and a thickness of the second oxide semiconductor layer is greater than 50 nm.

20. The integrated circuit structure as claimed in claim 13, wherein a carrier concentration of the first oxide semiconductor layer is different to that of the second oxide semiconductor layer.

21. The integrated circuit structure as claimed in claim 13, wherein a portion of the first source and the first drain directly contacting the first oxide semiconductor layer is composed of a Ti-containing metal, and a portion of the second source and the second drain directly contacting the second oxide semiconductor layer is composed of a none-Ti-containing metal.

22. The integrated circuit structure as claimed in claim 13, wherein a portion of the first source and the first drain directly contacting the first oxide semiconductor layer is composed of a none-Ti-containing metal, and a portion of the second source and the second drain directly contacting the second oxide semiconductor layer is composed of a Ti-containing metal.

23. An integrated circuit structure, at least comprising:

a substrate;

a first insulating layer, disposed on the substrate;

a second insulating layer, disposed on the substrate, and the first insulating layer being located between the second insulating layer and the substrate;

a first transistor, at least comprising;

a first gate, disposed between the first insulating layer and the substrate;

a first oxide semiconductor layer, the first insulating layer being disposed between the first gate and the first oxide semiconductor layer, and an area of the first gate being partially overlapped to that of the first oxide semiconductor layer;

a first source, connected to the first oxide semiconductor layer;

a first drain, connected to the first oxide semiconductor layer, and the first source and the first drain being respectively located at two sides of the first gate;

a second transistor, electrically connected to the first transistor, and comprising;

a second gate, disposed on the second insulating layer at a side departing from the substrate;

a second oxide semiconductor layer, the second insulating layer being disposed between the second gate and the second oxide semiconductor layer, and an area of the second gate being partially overlapped to that of the second oxide semiconductor layer, wherein a carrier concentration of the first oxide semiconductor layer is different to that of the second oxide semiconductor layer;

a second source, connected to the second oxide semiconductor layer; and

a second drain, connected to the second oxide semiconductor layer, and the second source and the second drain being respectively located at two sides of the second gate.

24. The integrated circuit structure as claimed in claim 23 further comprising a connecting metal connected between the first transistor and the second transistor.

25. The integrated circuit structure as claimed in claim 23, wherein a material of the first oxide semiconductor layer and the second oxide semiconductor layer comprises zinc oxide, indium gallium zinc oxide or indium zinc tin oxide.

26. The integrated circuit structure as claimed in claim 23, wherein the substrate is a flexible substrate.

27. The integrated circuit structure as claimed in claim 26, wherein a material of the flexible substrate comprises polyimide, PEN or PET.

28. The integrated circuit structure as claimed in claim 23, wherein a portion of the first source and the first drain directly contacting the first oxide semiconductor layer is composed of a Ti-containing metal, and a portion of the second source and the second drain directly contacting the second oxide semiconductor layer is composed of a none-Ti-containing metal.

29. The integrated circuit structure as claimed in claim 28, wherein a thickness of the first oxide semiconductor layer is different to that of the second oxide semiconductor layer.

30. The integrated circuit structure as claimed in claim 28, wherein a thickness of the first oxide semiconductor layer is greater than 50 nm, and a thickness of the second oxide semiconductor layer is less than 50 nm.

31. The integrated circuit structure as claimed in claim 23, wherein a portion of the first source and the first drain directly contacting the first oxide semiconductor layer is composed of a none-Ti-containing metal, and a portion of the second source and the second drain directly contacting the second oxide semiconductor layer is composed of a Ti-containing metal.

32. The integrated circuit structure as claimed in claim 31, wherein a thickness of the first oxide semiconductor layer is different to that of the second oxide semiconductor layer.

33. The integrated circuit structure as claimed in claim 31, wherein a thickness of the first oxide semiconductor layer is less than 50 nm, and a thickness of the second oxide semiconductor layer is greater than 50 nm.