Semiconductor device and method of manufacturing semiconductor device

• US 20100148171A1
• Filed: 12/14/2009
• Published: 06/17/2010
• Est. Priority Date: 12/15/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Hayashi, Yoshihiro, Inoue, Naoya, Kaneko, Kishou
• Granted Patent: US 8,378,341 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/242 AIBVI or AIBVII compounds, e.g. Cu2O, Cu I H01L29/247 takes precedence
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42352 with the gate at least partly formed in a trench
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a first interconnect layer which includes an insulating layer formed over said semiconductor substrate, and a first interconnect filled in a surficial portion of said insulating layer;

a semiconductor layer positioned over said first interconnect layer;

a gate insulating film positioned over or below said semiconductor layer; and

a gate electrode positioned on the opposite side of said semiconductor layer while placing said gate insulating film in between.

2. The semiconductor device as claimed in claim 1,

further comprising a second interconnect layer which is positioned over said first interconnect layer, and has a second interconnect connected to said semiconductor layer.

3. The semiconductor device as claimed in claim 1,

wherein said gate insulating film is positioned over said first interconnect layer, and between said semiconductor layer and said first interconnect layer, and

said gate electrode is formed in the same layer with said first interconnect.

4. The semiconductor device as claimed in claim 3,

wherein said first interconnect is a copper interconnect,

said gate insulating film functions as a diffusion blocking film, and

said semiconductor layer is formed over said diffusion blocking film.

5. The semiconductor device as claimed in claim 3,

wherein said semiconductor layer includes a channel region formed in said semiconductor layer, and

the semiconductor device further comprising:

a trapping film positioned over said semiconductor layer; and

a back-gate electrode positioned over said trapping film, and overlaps with said channel region in a plan view.

6. The semiconductor device as claimed in claim 5,

wherein said semiconductor layer, said gate insulating film, said gate electrode, said trapping film, and said back-gate electrode configure a memory element.

7. The semiconductor device as claimed in claim 1,

wherein said gate insulating film and said gate electrode are positioned over said semiconductor layer.

8. The semiconductor device as claimed in claim 1,

wherein said semiconductor layer has an oxide semiconductor layer.

9. The semiconductor device as claimed in claim 8,

wherein said oxide semiconductor layer is an InGaZnO layer or a ZnO layer.

10. The semiconductor device as claimed in claim 1,

wherein said insulating layer is a low-k insulating layer including a dielectric constant smaller than that of silicon oxide.

11. The semiconductor device as claimed in claim 1,

further comprising a MOS transistor-type element formed on said semiconductor substrate.

12. The semiconductor device as claimed in claim 11,

wherein at least a part of said MOS transistor-type element overlaps with said semiconductor layer in a plan view.

13. A method of manufacturing a semiconductor device comprising:

forming, over a semiconductor substrate, a first interconnect layer which includes an insulating layer, and a first interconnect filled in a surficial portion of said insulating layer;

forming, over said first interconnect layer, a gate insulating film which is positioned over said first interconnect;

forming a semiconductor layer over said gate insulating film; and

forming source-and-drain regions in said semiconductor layer.

14. The method of manufacturing a semiconductor device as claimed in claim 13,

further comprising, after said forming said semiconductor layer, forming a trapping film over said semiconductor layer;

and

forming a back-gate electrode over said trapping film, so as to overlap with said first interconnect in a plan view.

15. The method of manufacturing a semiconductor device as claimed in claim 14,

wherein said forming said trapping film and said forming said back-gate electrode precede said forming said source-and-drain regions, and

said forming said source-and-drain regions is a step of processing said semiconductor layer, using said back-gate electrode as a mask.

17. The method of manufacturing a semiconductor device as claimed in claim 13,

wherein said insulating layer is a low-k insulating layer including a dielectric constant smaller than that of silicon oxide.

18. The method of manufacturing a semiconductor device as claimed in claim 13,

wherein said semiconductor layer is an oxide semiconductor layer, and

heating, in said forming said semiconductor layer, said semiconductor substrate at a temperature of 400°

C. or lower.

19. The method of manufacturing a semiconductor device as claimed in claim 18,

wherein said forming said source-and-drain regions is a step of treating said semiconductor layer using a reductive plasma.

20. The method of manufacturing a semiconductor device as claimed in claim 18,

wherein said forming said source-and-drain regions is a step of selectively introducing an impurity into said semiconductor layer.

16. A method of manufacturing a semiconductor device comprising:

forming, over a semiconductor substrate, a first interconnect layer which includes an insulating layer, and a first interconnect filled in a surficial portion of said insulating layer;

forming a semiconductor layer over said first interconnect layer;

forming a gate insulating film over said semiconductor layer;

forming a gate electrode over said gate insulating film; and

forming source-and-drain regions in said semiconductor layer.