Graded high germanium compound films for strained semiconductor devices

• US 20100148217A1
• Filed: 12/11/2008
• Published: 06/17/2010
• Est. Priority Date: 12/11/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Simonelli, Danielle, Murthy, Anand
• Granted Patent: US 7,902,009 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.

Claims

1. A method of forming a crystalline compound film, comprising:

selectively forming a low germanium content seed layer;

selectively forming a transition layer on the low germanium content seed layer;

the transition layer formed while decrementing a process temperature from a first temperature to a second temperature; and

selectively forming a high germanium content layer on the transition layer.

2. The method of claim 1, wherein the transition layer is formed while decrementing a dichlorosilane, hydrogen chloride, and germane flow from a higher flow to a lower flow.

3. The method of claim 2, wherein the transition layer is formed while increasing a diborane flow from a lower flow to a higher flow.

4. The method of claim 3, wherein the first temperature is selected from a range between 700°

C. and 800°

C.

5. The method of claim 4, wherein the second temperature is between 25 to 100°

C. lower than the first temperature.

6. The method of claim 5, wherein the low germanium content seed layer is doped with boron to a concentration ranging between 5.0×

10¹⁹ atoms/cm³ to 1.5×

10²⁰ atoms/cm³.

7. The method of claim 6, wherein the high germanium content layer is doped with boron to a concentration ranging between 2.0×

10²⁰ atoms/cm³ to 3.0×

10²⁰ atoms/cm³.

8. A method comprising:

forming a gate stack and a pair of spacers on a multi-gate body, wherein the spacers are formed on laterally opposite sides of the gate stack;

etching the multi-gate body at regions adjacent to the spacers; and

selectively depositing a graded high-germanium content silicon germanium stack to form a source region and a drain region directly adjacent to the multi-gate body.

9. The method of claim 8, wherein the graded high-germanium content silicon germanium stack is formed of a silicon-germanium seed layer, a transition layer, and a high germanium content layer.

10. The method of claim 9, wherein the transition layer is formed while decrementing a dichlorosilane, hydrogen chloride, and germane flow from a higher flow to a lower flow.

11. The method of claim 10, wherein the transition layer is formed while increasing a diborane flow from a lower flow to a higher flow.

12. The method of claim 12, wherein the transition layer is formed beginning with a first temperature selected from a range between 700°

C. and 800°

C.

13. The method of claim 12, wherein the transition layer is formed ending with a second temperature selected from a range between 25 to 100°

C. lower than the first temperature

14. A transistor comprising:

a gate stack formed on a substrate;

spacers formed on laterally opposite sides of the gate stack; and

a source region and a drain region formed on the substrate adjacent and subjacent to the spacers, the source region and the drain region comprising a silicon-germanium seed layer, a transition layer, and a high germanium content layer.

15. The transistor of claim 14, wherein a lower portion of the transition layer has a germanium content ranging between 20-25 atomic weight % and an upper portion of the transition layer has a germanium content ranging between 40-55 atomic weight %.

16. The transistor of claim 14, wherein the silicon-germanium seed layer is doped with boron to a concentration ranging between 5.0×

10¹⁹ atoms/cm³ to 15×

10²⁰ atoms/cm³.

17. The transistor of claim 15, wherein the high germanium content layer is doped with boron to a concentration ranging between 2.0×

10²⁰ atoms/cm³ to 3.0×

10²⁰ atoms/cm³.

18. The transistor of claim 15, wherein a thickness of the transition layer is selected from a range between 150 Å

and 450 Å

.

19. The transistor of claim 18, wherein a thickness of the silicon-germanium seed layer is selected from a range between 100Å

-300 Å

.

20. The transistor of claim 19, wherein a thickness of the high germanium content layer is selected from a range between 300 Å

-600 Å

.