GATE STRUCTURE OF SEMICONDUCTOR DEVICE AND METHODS OF FORMING WORD LINE STRUCTURE AND MEMORY

• US 20100148239A1
• Filed: 12/12/2008
• Published: 06/17/2010
• Est. Priority Date: 12/12/2008
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lai, Erh-Kun, Lue, Hang-Ting
• Granted Patent: US 8,288,815 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A gate structure for a semiconductor device is provided. The gate structure includes a conductive structure. The conductive structure insulatively disposed over a substrate includes a middle portion and two spacer portions. The middle portion has a first surface and two second surfaces. The first surface is between the two second surfaces. The two spacer portions are respectively connected to the two second surfaces of the middle portion. A width of each of the two spacer portions gradually increases from top to bottom.

Claims

1. A gate structure for a semiconductor device, the gate structure comprising:

a conductive structure insulatively disposed over a substrate, the conductive structure comprising;

a middle portion having a first surface and two second surfaces, wherein the first surface is between the two second surfaces; and

two spacer portions respectively connected to the two second surfaces of the middle portion, wherein a width of each of the two spacer portions gradually increases from top to bottom.

2. The gate structure according to claim 1, wherein the gate structure further comprises a mask layer disposed on the middle portion of the conductive structure, and two sides of the mask layer are respectively enclosed by the two spacer portions of the conductive structure so that the mask layer is embedded into the conductive structure.

3. The gate structure according to claim 1, wherein an inner surface of each of the two spacer portions contacts with the middle portion, and an outer surface of each of the two spacer portions opposite the inner surface of each of the two spacer portions is a curved surface.

4. The gate structure according to claim 1, wherein the semiconductor device comprises a dielectric layer disposed on the substrate, the conductive structure is disposed on the dielectric layer, and the dielectric layer comprises a charge trapping layer for storing charges.

5. The gate structure according to claim 4, wherein the dielectric layer further comprises at least one of a tunneling layer and a blocking layer, the tunneling layer is disposed between the substrate and the charge trapping layer, and the blocking layer is disposed between the charge trapping layer and the conductive structure.

6. A method of forming a memory, the method comprising the steps of:

(a) forming a first dielectric layer, a conductive layer and a first mask layer on a substrate, wherein the first mask layer has two first openings for exposing a portion of the conductive layer;

(b) etching the conductive layer according to a pattern of the first mask layer so as to form two first grooves at the portion of the conductive layer, wherein a bottom surface and side surfaces of each of the two first grooves expose the conductive layer, and an interval between the side surfaces of each of the two first grooves is greater than a width of each of the two first openings;

(c) covering a conformal layer over the first mask layer and the two first grooves positioned on the conductive layer, wherein the conformal layer filled into each of the two first grooves has a void; and

(d) anisotropically etching the conformal layer, and etching the conductive layer and the first dielectric layer along the voids in the two first grooves until the substrate and the first mask layer are exposed so that a word line structure is formed.

7. The method according to claim 6, wherein the word line structure comprises the first mask layer, the remained conductive layer and the remained conformal layer, and the remained conformal layer is formed on two sides of the remained conductive layer so that a width of the word line structure gradually increases from top to bottom.

8. The method according to claim 6, wherein the step (b) comprises:

(b1) performing an anisotropic etching process so as to form two notches at the portion of the conductive layer, wherein a bottom surface and side surfaces of each of the two notches expose the conductive layer, and an interval between the side surfaces of each of the two notches is substantially equal to the width of each of the two first openings; and

(b2) performing an isotropic etching process to etch the side surfaces of each of the two notches so as to form the two first grooves.

9. The method according to claim 8, wherein the conductive layer comprises a first conductive portion and a second conductive portion, and the step (a) comprises:

(a1) sequentially forming the first dielectric layer, the first conductive portion and a second mask layer on the substrate, wherein the second mask layer has two second openings for exposing a portion of the first conductive portion, and an extending direction of each of the two second openings is substantially perpendicular to an extending direction of each of the two first openings;

(a2) performing an etching process to form two second grooves at the portion of the first conductive portion, wherein a bottom surface of each of the two second grooves exposes the substrate;

(a3) implanting a dopant into the exposed substrate to form a doped region;

(a4) filling a second dielectric layer into each of the two second grooves;

(a5) removing the second mask layer and a portion of the second dielectric layer to expose another portion of the first conductive portion and the remained second dielectric layer, wherein the remained second dielectric layer is higher than the first conductive portion; and

(a6) sequentially covering the second conductive portion and the first mask layer;

wherein the second conductive portion of the conductive layer is etched to a height of the remained second dielectric layer in the step (b1).

10. The method according to claim 6, wherein the conformal layer is covered with substantially the same thickness in the step (c).

11. The method according to claim 6, wherein the conformal layer and the first dielectric layer are etched by way of reactive ion etching (RIE) in the step (d).

12. The method according to claim 6, wherein the conductive layer comprises a first conductive portion and a second conductive portion, and the step (a) comprises.

(a1) sequentially forming the first dielectric layer, the first conductive portion and a second mask layer on the substrate, wherein the second mask layer has two second openings for exposing a portion of the first conductive portion, and an extending direction of each of the two second openings is substantially perpendicular to an extending direction of each of the two first openings;

(a2) performing an etching process to form two second grooves at the portion of the first conductive portion, wherein a bottom surface of each of the two second grooves exposes the substrate;

(a3) implanting a dopant into the exposed substrate to form a doped region;

(a4) filling a second dielectric layer into each of the two second grooves;

(a5) removing the second mask layer and a portion of the second dielectric layer to expose another portion of the first conductive portion and the remained second dielectric layer, wherein the remained second dielectric layer is higher than the first conductive portion; and

(a6) sequentially covering the second conductive portion and the first mask layer.

13. The method according to claim 6, wherein the conformal layer is composed of a conductive material.

14. The method according to claim 6, wherein the first dielectric layer comprises a charge trapping layer for storing charges.

15. The method according to claim 14, wherein the first dielectric layer further comprises a tunneling layer and a blocking layer, and the tunneling layer, the charge trapping layer and the blocking layer are sequentially formed on the substrate in the step (a) of forming the first dielectric layer.

16. A method of forming a word line structure, the method comprising the steps of:

(a) forming a conductive layer and a first mask layer on a substrate, wherein the first mask layer has a opening for exposing a portion of the conductive layer;

(b) etching the conductive layer according to a pattern of the first mask layer so as to form a groove at the portion of the conductive layer, wherein a bottom surface and side surfaces of the groove expose the conductive layer, and an interval between the side surfaces of the groove is greater than a width of the opening;

(c) covering a conformal layer over the first mask layer and the groove positioned on the conductive layer, wherein the conformal layer filled into the groove has a void; and

(d) anisotropically etching the conformal layer and etching the conductive layer along the void in the groove until the substrate and the first mask layer are exposed.

17. The method according to claim 16, wherein the word line structure comprises the first mask layer, the remained conductive layer and the remained conformal layer, and the remained conformal layer is formed on two sides of the remained conductive layer so that a width of the word line structure gradually increases from top to bottom.

18. The method according to claim 16, wherein the step (b) comprises:

(b1) performing an anisotropic etching process so as to form a notch at the portion of the conductive layer, wherein a bottom surface and side surfaces of each of the notch expose the conductive layer, and an interval between the side surfaces of each of the notch is substantially equal to the width of the opening; and

(b2) performing an isotropic etching process to etch the side surfaces of the notch so as to form the groove.

19. The method according to claim 16, wherein the conformal layer is covered with substantially the same thickness in the step (c).

20. The method according to claim 16, wherein the conformal layer is etched by way of reactive ion etching (RIE) in the step (d).

21. The method according to claim 16, wherein the conformal layer is composed of a conductive material.

22. A semiconductor device, comprising:

a substrate;

a dielectric layer formed on the substrate; and

a plurality of gate structures, each of which comprises;

a conductive structure disposed over the dielectric layer, wherein the conductive structure comprises a middle portion and two spacer portions, the middle portion has a first surface and two second surfaces, wherein the first surface is between the two second surfaces, the two spacer portions are respectively connected to the two second surfaces of the middle portion, and a width of each of the two spacer portions gradually increases from top to bottom.

23. The semiconductor device according to claim 22, wherein each of the gate structures further comprises a mask layer disposed on the middle portion of the conductive structure, and two sides of the mask layer are respectively enclosed by the two spacer portions of the conductive structure so that the mask layer is embedded into the conductive structure.

24. The semiconductor device according to claim 22, wherein an inner surface of each of the two spacer portions contacts with the middle portion, and an outer surface of each of the two spacer portions opposite the inner surface of each of the two spacer portions is a curved surface.

25. The semiconductor device according to claim 22, wherein the dielectric layer comprises a charge trapping layer for storing charges.

26. The semiconductor device according to claim 25, wherein the dielectric layer further comprises at least one of a tunneling layer and a blocking layer the tunneling layer is disposed between the substrate and the charge trapping layer, and the blocking layer is disposed between the charge trapping layer and the conductive structure.

27. The semiconductor device according to claim 22, wherein when a voltage is applied to the gate structures, an inversion area is formed in the substrate between the two adjacent gate structures.

28. The semiconductor device according to claim 22, further comprising two doped regions respectively located in the substrate on two sides of the gate structure.

29. The semiconductor device according to claim 22 is a NAND array memory.

30. The semiconductor device according to claim 22 is a PACAND array memory.

31. The semiconductor device according to claim 22 is a virtual ground array memory.