TUNABLE SPACERS FOR IMPROVED GAPFILL

• US 20100148269A1
• Filed: 12/17/2008
• Published: 06/17/2010
• Est. Priority Date: 12/17/2008
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: YELEHANKA, Ramachandramurthy Pradeep, NAGARAD, Sripad, MISHRA, Shailendra
• Granted Patent: US 8,236,678 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A device that includes a substrate with an active region is disclosed. The device includes a gate disposed in the active region and tunable sidewall spacers on sidewalls of the gate. A profile of the tunable sidewall spacers includes upper and lower portions in which width of the spacers in the upper portion is reduced at a greater rate than the lower portion.

Claims

1. A method for forming a device comprising:

providing a substrate with an active region, the substrate is prepared with a gate;

forming sidewall spacers on sidewall of the gate; and

performing a tuning process on the spacers to produce a profile wherein width of the spacers in an upper portion is reduced at a greater rate than a lower portion.

2. The method of claim 1 wherein forming the sidewall spacers comprises:

depositing a spacer layer to cover the substrate and gate; and

patterning the spacer layer to remove horizontal components, leaving sidewall spacers on the sidewall of the gate.

3. The method of claim 2 wherein the sidewall spacers comprises hexochlorosilane (HCD) silicon nitride.

4. The method of claim 2 wherein the sidewall spacers comprise HCD silicon nitride doped with etch rate controlling (ERC) dopants to produce an etch rate differential between the upper portion and lower portion in the tuning process.

5. The method of claim 4 wherein the ERC dopant comprises carbon.

6. The method of claim 2 wherein the spacer layer comprises an etch rate differential between the upper portion and lower portion in the tuning process.

7. The method of claim 6 wherein the etch rate differential comprises an etch rate in the upper portion which is higher than an etch rate in the lower portion.

8. A method for forming tunable sidewall spacers comprising:

providing a substrate having a feature thereon;

forming a dielectric layer on the substrate covering the feature; and

patterning the dielectric layer to form tunable sidewall spacers, wherein a width of the spacers in an upper portion is reduced at a greater rate than a lower portion in a tuning process.

9. The method of claim 8 wherein the dielectric layer comprises HCD silicon nitride.

10. The method of claim 8 wherein the dielectric layer comprises HCD silicon nitride doped with ERC dopants to produce an etch rate differential between the upper portion and lower portion in the tuning process.

11. The method of claim 10 wherein the ERC dopant comprises carbon.

12. The method of claim 8 wherein the dielectric spacer layer comprises an etch rate differential between the upper portion and lower portion in the tuning process.

13. The method of claim 12 wherein the etch rate differential comprises an etch rate in the upper portion which is higher than an etch rate in the lower portion.

14. A device comprising:

a substrate with an active region;

a gate disposed in the active region; and

tunable sidewall spacers on sidewalls of the gate, wherein a profile of the tunable sidewall spacers comprises upper and lower portions in which width of the spacers in the upper portion is reduced at a greater rate than the lower portion.

15. The device of claim 14 wherein the tunable sidewall spacers comprise HCD silicon nitride.

16. The device of claim 14 wherein the tunable sidewall spacers comprise HCD silicon nitride doped with ERC dopant.

17. The device of claim 16 wherein concentration of the ERC dopant affects etch rate of the tunable sidewall spacer.

18. The device of claim 17 wherein the concentration of the ERC dopant is inversely related to the etch rate of the tunable sidewall spacer.

19. The device of claim 16 wherein the ERC dopant comprises carbon.

20. The device of claim 14 wherein the tunable sidewall spacers comprise an initial width ratio of the upper and lower portions (W_IU/W_IL) which is greater than final width ratio of the upper and lower portions (W_FU/W_FL).

21. The device of claim 20 wherein the W_IU/W_IL is greater W_FU/W_FL by at least 0.1-0.9.