SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20100148303A1
• Filed: 11/05/2009
• Published: 06/17/2010
• Est. Priority Date: 12/11/2008
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Nishiura, Shinji
• Application Number:
  US12/613,237
• Publication Number:
  US 20100148303A1
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes: a semiconductor substrate; an interlayer insulating film formed on the semiconductor substrate; a first inductor interconnect layer having a spiral pattern, formed to be embedded in a top portion of the interlayer insulating film; a barrier insulating film formed to cover the interlayer insulating film and the first inductor interconnect layer, the barrier insulating film having at least one connecting groove running along the first inductor interconnect layer; and a second inductor interconnect layer formed on the barrier insulating film to run along the first inductor interconnect layer and fill the connecting groove to be electrically connected with the first inductor interconnect layer. The second inductor interconnect layer has at least one concave groove formed on the top to run along the length thereof.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

an interlayer insulating film formed on the semiconductor substrate;

a first inductor interconnect layer having a spiral pattern, formed to be embedded in a top portion of the interlayer insulating film;

a barrier insulating film formed to cover the interlayer insulating film and the first inductor interconnect layer, the barrier insulating film having at least one connecting groove extending vertically therethrough and running along the first inductor interconnect layer; and

a second inductor interconnect layer formed on the barrier insulating film to run along the first inductor interconnect layer and fill the connecting groove to be electrically connected with the first inductor interconnect layer, wherein

the second inductor interconnect layer has at least one concave groove formed on the top to run along a length direction of the second inductor interconnect layer.

2. The device of claim 1, further comprising:

an interconnect layer formed below the first inductor interconnect layer and electrically connected with an inner end of the first inductor interconnect layer via at least one metal via,

wherein

the interconnect layer is drawn outside the spiral pattern.

3. The device of claim 1, wherein

the concave groove is located above the connecting groove.

4. The device of claim 1, wherein

a plurality of connecting grooves and a plurality of concave grooves are provided.

5. The device of claim 1, wherein

the thickness of the second inductor interconnect layer is greater than the thickness of the first inductor interconnect layer and smaller than the width of the connecting groove.

6. The device of claim 1, further comprising:

a topmost interconnect layer formed to be embedded in the top portion of the interlayer insulating film and made of the same material as the first inductor interconnect layer; and

a pad electrode formed on the barrier insulating film and made of the same material as the second inductor interconnect layer.

7. The device of claim 1, wherein

the first inductor interconnect layer includes a Cu film, and

the second inductor interconnect layer includes an Al film or an AlCu film.

8. A method for fabricating a semiconductor device, comprising the steps of:

(a) forming an interlayer insulating film on a semiconductor substrate;

(b) forming a first inductor interconnect layer having a spiral pattern to be embedded in a top portion of the interlayer insulating film;

(c) forming a barrier insulating film covering the interlayer insulating film and the first inductor interconnect layer;

(d) forming at least one connecting groove through the barrier insulating film to extend vertically therethrough and run along the first inductor interconnect layer; and

(e) forming a second inductor interconnect layer on the barrier insulating film to run along the first inductor interconnect layer and fill the connecting groove to be electrically connected with the first inductor interconnect layer,

wherein

in the step (e), at least one concave groove is formed on the top of the second inductor interconnect layer to run along the length of the second inductor interconnect layer.

9. The method of claim 8, wherein

the step (e) includes the step of depositing a film made of Al or AlCu in the connecting groove and on the barrier insulating film by low-temperature sputtering and then forming the film into a predetermined pattern.

10. The method of claim 9, wherein

the low-temperature sputtering is conducted at a temperature between 100°

C. and 150°

C. inclusive.

11. The method of claim 8, wherein

the step (e) includes the step of forming a film made of Al or AlCu in the connecting groove and on the barrier insulating film and then etching away a top portion of the film in a predetermined region to form the concave groove.

12. The method of claim 8, wherein

in the step (b), a topmost interconnect layer made of the same material as the first inductor interconnect layer is formed to be embedded in a top portion of the interlayer insulating film, and

in the step (e), a pad electrode made of the same material as the second inductor interconnect layer is formed on the barrier insulating film.

13. The method of claim 8, further comprising the steps of:

forming another interlayer insulating film and an interconnect layer embedded in a top portion of the another interlayer insulating film on the semiconductor substrate before the step (a); and

forming at least one metal via through the interlayer insulating film for electrically connecting the interconnect layer with the first inductor interconnect layer, wherein

the interconnect layer is drawn outside the spiral pattern.