Stacked Die Parallel Plate Capacitor

• US 20100148373A1
• Filed: 12/17/2008
• Published: 06/17/2010
• Est. Priority Date: 12/17/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chandrasekaran, Arvind
• Granted Patent: US 8,310,061 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A stacked integrated circuit having a first die with a first surface and a second die with a second surface facing the first surface, the stacked integrated circuit includes a capacitor. The capacitor is formed by a first conducting plate on a region of the first surface, a second conducting plate on a region of the second surface substantially aligned with the first conducting plate, and a dielectric between the first conducting electrode and the second conducting electrode.

Claims

1. A stacked integrated circuit having a first die with a first surface and a second die with a second surface facing the first surface, the stacked integrated circuit comprising:

a capacitor formed by a first conducting plate on a region of the first surface, a second conducting plate on a region of the second surface substantially aligned with the first conducting plate, and a dielectric between the first conducting electrode and the second conducting electrode.

2. The stacked integrated circuit of claim 1, in which the first conducting plate is copper.

3. The stacked integrated circuit of claim 1, in which the dielectric comprises a mold compound.

4. The stacked integrated circuit of claim 1, in which a space between the first conducting plate and the second conducting plate is five to thirty micrometers.

5. The stacked integrated circuit of claim 1, in which the thickness of the first conducting plate is less than 1 micron.

6. The stacked integrated circuit of claim 1, in which the thickness of the second conducting plate is less than 1 micron.

7. The stacked integrated circuit of claim 1, in which the first die further comprises through silicon vias.

8. The stacked integrated circuit of claim 7, in which the through silicon vias couple to the first conducting plate.

9. The integrated circuit of claim 1, further comprising a packaging substrate bonded to the first die.

10. The integrated circuit of claim 9, in which the integrated circuit is a flip-chip.

11. The integrated circuit of claim 1, in which the first surface of the first die further comprises microbumps coupling the first die to the second die.

12. The integrated circuit of claim 11, in which the first conducting plate on the first surface is located in a periphery of the stacked IC.

13. The integrated circuit of claim 11, in which the second conducting plate on the second surface is located in a periphery of the stacked IC.

14. The integrated circuit of claim 1, in which the first die further comprises a microprocessor.

15. The integrated circuit of claim 1, in which the second die further comprises memory circuitry.

16. The integrated circuit of claim 1, in which the integrated circuit is incorporated into a communications device.

17. A stacked integrated circuit, comprising:

a first die, having a first surface comprising a first conducting plate;

a second die stacked with the first die, the second die having a second surface facing the first surface of the first die, the second surface comprising a second conducting plate opposing the first conducting plate; and

an insulator between the first die and the second die,

wherein the first conducting plate, the second conducting plate, and the insulator form a capacitor.

18. The stacked integrated circuit of claim 17, in which the space between the first conducting plate and the second conducting plate is ten to thirty micrometers.

19. The stacked integrated circuit of claim 17, in which the thickness of the first conducting plate is less than 1 micron.

20. The stacked integrated circuit of claim 17, in which the thickness of the second conducting plate is less than 1 micron.