LIMITER AND SEMICONDUCTOR DEVICE USING THE SAME
First Claim
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1. A semiconductor device comprising a limiter, the limiter including:
- a transistor including a first gate and a second gate,wherein a drain of the transistor is connected to the second gate;
wherein the drain and the second gate are connected to an input terminal and an output terminal;
wherein the first gate is capable of being in an electrically floating state; and
wherein the limiter is configured to change a limit voltage by controlling an amount of charge accumulated in the first gate by adjusting a second gate voltage and a source voltage of the transistor.
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Abstract
The limiter of the invention uses as a diode a stacked gate thin film transistor (TFT) including a floating gate. When the TFT including a floating gate is used, the threshold voltage Vth may be corrected by controlling the amount of charge accumulated in the floating gate even in the case where there are variations in the threshold voltages Vth of the TFT.
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Citations
20 Claims
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1. A semiconductor device comprising a limiter, the limiter including:
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a transistor including a first gate and a second gate, wherein a drain of the transistor is connected to the second gate; wherein the drain and the second gate are connected to an input terminal and an output terminal; wherein the first gate is capable of being in an electrically floating state; and wherein the limiter is configured to change a limit voltage by controlling an amount of charge accumulated in the first gate by adjusting a second gate voltage and a source voltage of the transistor. - View Dependent Claims (5, 9, 13, 17)
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2. A semiconductor device comprising a limiter, the limiter including:
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at least two transistors, each including a first gate and a second gate, wherein a drain and the second gate of each of the at least two transistors are connected to each other; wherein the at least two transistors are connected in series so as to have the same forward current direction; wherein the drain and the second gate of one of the at least two transistors are connected to an input terminal and an output terminal, wherein the first gate of each of the at least two transistors is capable of being in an electrically floating state, and wherein the limiter is configured to change a limit voltage by controlling an amount of charge accumulated in the first gates of the at least two transistors by adjusting second gates voltages and sources voltages of the at least two transistors. - View Dependent Claims (6, 10, 14, 18)
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3. A semiconductor device comprising a limiter, the limiter including:
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a first transistor including a first gate and a second gate; and a second transistor; wherein a drain and the second gate of the first transistor are connected to each other; wherein a drain and a gate of the second transistor are connected to each other; wherein the first transistor and the second transistor are connected in series so as to have the same forward current direction; wherein the drain of the second transistor and the second gate are connected to an input terminal and an output terminal, wherein the first gate of the first transistor is capable of being in an electrically floating state, and wherein the limiter is configured to change a limit voltage by controlling an amount of charge accumulated in the first gate by adjusting a second gate voltage and a source voltage of the first transistor. - View Dependent Claims (7, 11, 15, 19)
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4. A semiconductor device comprising:
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an integrated circuit, and an antenna connected to the integrated circuit, wherein the integrated circuit includes a limiter including a transistor, the transistor including a first gate and a second gate, wherein a drain of the transistor is connected to the second gate; wherein the drain and the second gate are connected to an input terminal and an output terminal; wherein the first gate is capable of being in an electrically floating state; and wherein the limiter is configured to change a limit voltage by controlling an amount of charge accumulated in the first gate by adjusting a second gate voltage and a source voltage of the transistor. - View Dependent Claims (8, 12, 16, 20)
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Specification