METHOD AND SYSTEM FOR POWER MANAGEMENT FOR A FREQUENCY SYNTHESIZER IN A GNSS RECEIVER CHIP

• US 20100149033A1
• Filed: 01/12/2009
• Published: 06/17/2010
• Est. Priority Date: 12/12/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Abraham, Charles
• Granted Patent: US 9,322,924 B2
• Time in Patent Office: Days
• US Class Current: 342/357.630
• CPC Class Codes: G01S 19/34 Power consumption

Abstract

A frequency synthesizer in a GNSS receiver chip enables duty cycling operation of the frequency synthesizer. The frequency synthesizer is cycled on to generate required clock signals for the GNSS receiver chip, and cycled off during a measurement duty cycle comprising measurement available intervals and measurement unavailable intervals. A reference clock inputted to the frequency synthesizer is on during the measurement duty-cycle. During the measurement available intervals, the frequency synthesizer is cycled on to generate the required clock based on the reference clock. During the measurement unavailable intervals, the frequency synthesizer is cycled off and clock timing is maintained based on the reference clock. A number of elapsed clock cycles of the reference clock is captured for a measurement unavailable interval and transferred to a clock offset. The GNSS receiver chip processes signals received using the required clock and the clock offset in a following measurement available interval.

Claims

1. A method for communication, the method comprising:

duty cycling operation of a frequency synthesizer within a GNSS RF front-end of a GNSS receiver chip, wherein said frequency synthesizer is cycled on to generate required clock signals for at least said GNSS receiver chip, and cycled off during a measurement duty cycle.

2. The method according to claim 1, wherein said measurement duty cycle comprises a plurality of measurement available intervals and a plurality of measurement unavailable intervals.

3. The method according to claim 2, wherein a reference clock inputted to said frequency synthesizer is on during entire said measurement duty cycle.

4. The method according to claim 3, comprising cycling on said frequency synthesizer to generate said required clock signals based on said reference clock during said plurality of measurement available intervals.

5. The method according to claim 4, comprising processing signals received by said wireless receiver using said required clock during said plurality of measurement available intervals.

6. The method according to claim 3, comprising cycling off said frequency synthesizer inside said GNSS receiver chip during said plurality of measurement unavailable intervals.

7. The method according to claim 6, comprising maintaining clock timing of said required clock signals based on said reference clock during said plurality of measurement unavailable intervals.

8. The method according to claim 7, comprising capturing number of elapsed clock cycles of said reference clock for a measurement unavailable interval of said measurement duty cycle.

9. The method according to claim 8, comprising transferring said captured number of elapsed clock cycles of said reference clock for said measurement unavailable interval of said measurement duty cycle to a clock offset.

10. The method according to claim 9, comprising:

cycling on said frequency synthesizer to generate said required clock signals in a measurement available interval immediately following said measurement unavailable interval of said measurement duty cycle; and

processing signals received by said GNSS receiver chip using said required clock signals with said clock offset.

11. A system for communication, the system comprising:

one or more circuits in a GNSS receiver chip, said one or more circuits comprising a GNSS front end and a frequency synthesizer, wherein said one or more circuits are operable to duty cycle operation of said frequency synthesizer within GNSS RF front-end of said GNSS receiver chip, and said frequency synthesizer is cycled on to generate required clock signals for at least said GNSS receiver chip, and cycled off during a measurement duty cycle.

12. The system according to claim 11, wherein said measurement duty cycle comprises a plurality of measurement available intervals and a plurality of measurement unavailable intervals.

13. The system according to claim 12, wherein a reference clock inputted to said frequency synthesizer is on during entire said measurement duty cycle.

14. The system according to claim 13, wherein said one or more circuits are operable to cycle on said frequency synthesizer inside said wireless receiver to generate said required clock signals based on said reference clock during said plurality of measurement available intervals.

15. The system according to claim 14, wherein said one or more circuits are operable to process signals received by said wireless receiver using said required clock during said plurality of measurement available intervals.

16. The system according to claim 13, wherein said one or more circuits are operable to cycle off said frequency synthesizer inside said GNSS receiver chip during said plurality of measurement unavailable intervals.

17. The system according to claim 16, wherein said one or more circuits are operable to maintain clock timing of said required clock signals based on said reference clock during said plurality of measurement unavailable intervals.

18. The system according to claim 17, wherein said one or more circuits are operable to capture number of elapsed clock cycles of said reference clock for a measurement unavailable interval of said measurement duty cycle.

19. The system according to claim 18, wherein said one or more circuits are operable to transfer said captured number of elapsed clock cycles of said reference clock for said measurement unavailable interval of said measurement duty cycle to a clock offset.

20. The system according to claim 19, wherein

said one or more circuits are operable to cycle on said frequency synthesizer to generate said required clock signals in a measurement available interval immediately following said measurement unavailable interval of said measurement duty cycle;

and

said one or more circuits are operable to process signals received by said GNSS receiver chip using said required clock signals with said clock offset.