Media Action Script Acceleration System

• US 20100149192A1
• Filed: 02/14/2009
• Published: 06/17/2010
• Est. Priority Date: 12/15/2008
• Status: Active Grant

• Current Assignee: LeoNovus USA, Inc. (LeoNovus, Inc.)
• Original Assignee: PersonalPath Systems, Inc. (Abbott Laboratories Incorporated)
• Inventors: Master, Paul L., Satyavolu, Lakshmikanth Surya Naga, Kota, Bhaskar, Bollam, Praveen Kumar, Sambaraju, Sairam, Puppala, Ganapathi Venkata
• Granted Patent: US 8,487,942 B2
• Time in Patent Office: Days
• US Class Current: 345/501
• CPC Class Codes: G06T 1/00 General purpose image data processing

Abstract

Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary system comprises: a network I/O interface; a frame buffer; a first memory; and a plurality of processors to separate the action script from other data, to convert a plurality of descriptive elements of the action script into a plurality of hardware-level operational or control codes, and to perform one or more operations corresponding to an operational code to generate pixel data for the graphical image. In an exemplary embodiment, at least one processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Claims

1. A system for processing an action script for a graphical image for visual display, the system comprising:

a network input and output interface to receive data;

a first memory to store data;

a frame buffer to store pixel data; and

a plurality of processors to convert a plurality of descriptive elements of the action script into a plurality of operational codes, to perform one or more operations corresponding to an operational code of the plurality of operational codes to generate pixel data for the graphical image, and to transfer the pixel data to the frame buffer.

2. The system of claim 1, further comprising:

a display controller coupled to the frame buffer to receive the pixel data; and

a display coupled to the display controller to visually display the graphical image.

3. The system of claim 1, further comprising:

a user input and output interface; and

an audio input and output interface.

4. The system of claim 1, wherein a first processor of the plurality of processors is to convert at least some descriptive elements of the plurality of descriptive elements of the action script into at least some operational codes and corresponding data, and a second processor of the plurality of processors is to perform at least one operation corresponding to an operational code of the plurality of operational codes using corresponding data to generate pixel data for the graphical image.

5. The system of claim 1, wherein a first processor of the plurality of processors is to convert at least some descriptive elements of the plurality of descriptive elements of the action script into at least some operational codes and corresponding data, and transfer at least some operational codes of the plurality of operational codes to a second processor and to a third processor of the plurality of processors, wherein the second processor is to perform a first operation corresponding to a first operational code of the plurality of operational codes using corresponding data and the third processor is to perform a second operation corresponding to a second operational code of the plurality of operational codes using corresponding data to generate pixel data for the graphical image.

6. The system of claim 1, wherein at least one processor of the plurality of processors is coupled to the first memory through at least one of the following:

an interconnection network, a configurable interconnect, a packet-based interconnect, a circuit-switched interconnect, a crosspoint switch, a serial bus, a parallel bus, or a network.

7. The system of claim 1, wherein a first processor of the plurality of processors is coupled to a second processor of the plurality of processors through at least one of the following:

the first memory, an interconnection network, a configurable interconnect, a packet-based interconnect, a circuit-switched interconnect, a crosspoint switch, a serial bus, a parallel bus, or a network.

8. The system of claim 1, wherein at least one processor of the plurality of processors further is to parse the action script into the plurality of descriptive elements and corresponding data.

9. The system of claim 8, wherein at least one processor of the plurality of processors further is to decode a descriptive element to determine a corresponding parsing operational code of the plurality of operational codes to control the parsing of the action script.

10. The system of claim 8, wherein the plurality of processors further comprise:

a decoder to determine a type of descriptive element;

a parsing controller to determine or select a number of bits to parse parameter;

a stream register to store a plurality of bits of the action script; and

at least one barrel shifter to shift out of the stream register a number of bits designated by the number of bits to parse parameter.

11. The system of claim 1, wherein at least one processor of the plurality of processors further is to parse the action script into a plurality of temporally descriptive elements, a plurality of positionally descriptive elements, and corresponding data.

12. The system of claim 1, wherein at least one processor of the plurality of processors further is to extract data from the action script and store in the first memory a plurality of control words comprising the extracted data in predetermined fields.

13. The system of claim 12, wherein the at least one processor of the plurality of processors further is to store the plurality of operational codes and plurality of control words in a database structure.

14. The system of claim 12, wherein each control word of the plurality of control words comprises a starting or an ending x-coordinate and y-coordinate for a corresponding line or curve segment for the graphical image.

15. The system of claim 14, wherein each control word of the plurality of control words further comprises a control x-coordinate and control y-coordinate for a corresponding curve segment for the graphical image.

16. The system of claim 12, wherein each control word of the plurality of control words comprises a first memory address for line style array for a corresponding line or curve segment for the graphical image and a second memory address for fill style array for a plurality of line or curve segments comprising the graphical image.

17. The system of claim 12, wherein each control word of the plurality of control words comprises a line style array for a corresponding line or curve segment for the graphical image and a fill style array for a plurality of line or curve segments comprising the graphical image.

18. The system of claim 1, wherein at least one processor of the plurality of processors further is to separate the action script from other data.

19. The system of claim 1, wherein the plurality of descriptive elements are a plurality of tags, or bytecodes, or a plurality of control tags, or a plurality of definition tags, or a plurality of dictionary tags, or a plurality of dictionary repositories.

20. The system of claim 1, further comprising:

a second memory to store the plurality of operational codes; and

wherein at least one processor of the plurality of processors further is to convert the action script directly to the plurality of operational codes by performing a deterministic function on each descriptive element of the plurality of descriptive elements to generate a corresponding result and to use the result to determine a corresponding operational code of the plurality of operational codes.

21. The system of claim 1, further comprising:

a second memory to store a look up table having the plurality of operational codes; and

wherein at least one processor of the plurality of processors further is to convert the action script directly to the plurality of operational codes by performing a hash function on each descriptive element of the plurality of descriptive elements to generate a corresponding hash result and to use the hash result as an index or entry into the look up table to determine a corresponding operational code of the plurality of operational codes.

22. The system of claim 1, wherein at least one processor of the plurality of processors further is to decode each operational code of the plurality of operational codes to generate a corresponding plurality of control signals to control circuitry to perform a selected operation, of a plurality of operations, corresponding to a selected operational code of the plurality of operational codes.

23. The system of claim 22, wherein at least one processor of the plurality of processors further comprises a floating point circuit, and wherein at least one processor of the plurality of processors further is to generate a first corresponding control signal to enable the floating point circuit to perform the selected operation.

24. The system of claim 23, wherein at least one processor of the plurality of processors further is to generate a second corresponding control signal to select a floating point calculation result provided by the enabled floating point circuit.

25. The system of claim 22, wherein at least one processor of the plurality of processors further comprises an arithmetic logic unit, and wherein at least one processor of the plurality of processors further is to decode an operational code of the plurality of operational codes to generate a corresponding plurality of control signals to select a calculation result generated by the arithmetic logic unit.

26. The system of claim 1, wherein at least one processor of the plurality of processors further comprises:

at least one arithmetic logic unit; and

at least one floating point circuit.

27. The system of claim 26, further comprising:

a configurable interconnect coupled to the at least one arithmetic logic unit and to the at least one floating point execution unit, the configurable interconnect comprising;

a multiport register; and

a cross-point switch for configuration of a data path.

28. The system of claim 1, wherein at least one processor of the plurality of processors further is to match a plurality of line or curve segments of a boundary of the graphical image.

29. The system of claim 28, wherein at least one processor of the plurality of processors further is to determine a sequential ordering of the plurality of line or curve segments to form boundary coordinates of the graphical image.

30. The system of claim 1, wherein at least one processor of the plurality of processors further is to apply a fill style to generate pixel data for an area of the graphical image.

31. The system of claim 30, wherein at least one processor of the plurality of processors further is to apply a line style by forming a second graphical image from a boundary of the graphical image, and wherein at least one processor of the plurality of processors further is to apply a fill style to the second graphical image to generate pixel data for the line style.

32. The system of claim 1, wherein at least one processor of the plurality of processors is to perform a Transmission Control Protocol (“

TCP”

), or Internet Protocol (“

IP”

), or both TCP and IP, for reception of a data file.

33. The system of claim 1, wherein at least one processor of the plurality of processors is to perform hypertext transfer protocol (“

HTTP”

) for reception of a data file.

34. The system of claim 33, wherein at least one processor of the plurality of processors further is to pre-fetch referenced data of the data file.

35. The system of claim 33, wherein at least one processor of the plurality of processors further is to generate pixel data for hypertext markup language (“

HTML”

) data, or extensible markup language (“

XML”

) data, or both HTML and XML data of the data file.

36. The system of claim 35, wherein at least one processor of the plurality of processors further is to transfer the pixel data for the HTML or XML data to the frame buffer.

37. The system of claim 35, further comprising:

a visual display;

wherein at least one processor of the plurality of processors further is to transfer the pixel data for the HTML or XML data to the visual display.

38. The system of claim 35, further comprising:

a display controller;

wherein at least one processor of the plurality of processors further is to transfer the pixel data for the HTML or XML data to the display controller.

39. The system of claim 1, wherein the plurality of descriptive elements are a specification of at least one graphical image at least partially in a non-pixel-by-pixel form.

40. The system of claim 1, wherein the plurality of descriptive elements are a specification of at least one graphical image in a form which at least partially is not a pixel bitmap and at least partially is not a pixel matrix.

41. The system of claim 1, wherein each operational code of the plurality of operational codes comprises at least one of the following:

a hardware-level instruction, or a hardware-level sub-instruction, or a hardware-level control code, or a hardware-level binary instruction, or hardware-level configuration, or a hardware-level control signal, or hardware-level microcode.

42. The system of claim 1, wherein at least one processor of the plurality of processors further comprises a hardware decoder to decode a selected operational code of the plurality of operational codes into at least one of the following:

a hardware-level instruction, or a hardware-level sub-instruction, or a hardware-level control code, or a hardware-level binary instruction, or hardware-level configuration, or a hardware-level control signal, or hardware-level microcode.

43. The system of claim 1, wherein the action script is a data file which has not been fully compiled to machine code and which comprises at least one descriptive element specifying the graphical image at least partially in a form which is not pixel-based.

44. The system of claim 1, wherein the action script is a data file specifying the graphical image at least partially using non-pixel data and which comprises an ASCII-encoded scripting language or bytecode.

45. The system of claim 1, wherein the graphical image is an image of any kind for visual display which has been specified at least partially in a form in the action script which is not a pixel bitmap and is not a pixel matrix.

46. The system of claim 1, wherein at least one processor of the plurality of processors is at least one of the following:

a field programmable gate array, an application-specific integrated circuit, a microprocessor, a processor core, a cell processor, a plurality of processor cores, a digital signal processor, a reduced instruction set processor, a reconfigurable processing element, a graphics processing unit, or a computing grid.

47. The system of claim 1, wherein the plurality of processors, the network input and output interface, the first memory, and the frame buffer are embodied in a single integrated circuit.

48. A system for processing an action script for a graphical image for visual display, the system comprising:

a network input and output interface to receive data;

a first memory circuit to store data;

a frame buffer to store pixel data; and

a plurality of processor circuits to separate the action script from other data, to parse the action script, to convert a plurality of descriptions of the action script into a plurality of operational codes, and to perform one or more operations in response to a selected operational code of the plurality of operational codes to generate pixel data for the graphical image.

49. The system of claim 48, further comprising:

a display controller coupled to the frame buffer to receive the pixel data; and

a display coupled to the display controller to visually display the graphical image.

50. The system of claim 48, further comprising:

a user input and output interface; and

an audio input and output interface.

51. The system of claim 48, wherein a first processor circuit of the plurality of processor circuits is to convert at least some descriptions of the plurality of descriptions of the action script into at least some operational codes and corresponding data, and a second processor circuit of the plurality of processor circuits is to perform at least one operation corresponding to an operational code of the plurality of operational codes using the corresponding data to generate pixel data for the graphical image.

52. The system of claim 48, wherein a first processor circuit of the plurality of processor circuits is to convert at least some descriptions of the plurality of descriptions of the action script into at least some operational codes and corresponding data, and transfer at least some operational codes of the plurality of operational codes to a second processor circuit and to a third processor circuit of the plurality of processor circuits, wherein the second processor circuit is to perform a first operation corresponding to a first operational code of the plurality of operational codes using corresponding data to generate pixel data for the graphical image and the third processor circuit is to perform a second operation corresponding to a second operational code of the plurality of operational codes using corresponding data to generate pixel data for the graphical image.

53. The system of claim 48, wherein at least one processor circuit of the plurality of processor circuits is coupled to the first memory circuit through at least one of the following:

an interconnection network, a configurable interconnect, a packet-based interconnect, a circuit-switched interconnect, a crosspoint switch, a serial bus, a parallel bus, or a network.

54. The system of claim 48, wherein a first processor circuit of the plurality of processor circuits is coupled to a second processor circuit of the plurality of processor circuits through at least one of the following:

the first memory circuit, an interconnection network, a configurable interconnect, a packet-based interconnect, a circuit-switched interconnect, a crosspoint switch, a serial bus, a parallel bus, or a network.

55. The system of claim 48, wherein at least one processor circuit of the plurality of processor circuits further is to parse the action script into the plurality of descriptions and corresponding data.

56. The system of claim 55, wherein at least one processor circuit of the plurality of processor circuits further is to decode a description of the plurality of descriptions to determine a corresponding parsing operational code of the plurality of operational codes to control the parsing of the action script.

57. The system of claim 56, wherein the plurality of processor circuits further comprise:

a parser circuit to parse the action script into the plurality of descriptions and the corresponding data;

a converter circuit to convert the plurality of descriptions of the action script into the plurality of operational codes; and

an execution circuit to use the corresponding data to perform the one or more operations in response to the selected operational code to generate the pixel data.

58. The system of claim 57, wherein at least one processor circuit of the plurality of processor circuits further comprises:

a decoder circuit to decode a description to determine a corresponding parsing operational code of the plurality of operational codes to control the parsing of the action script by the parser circuit.

59. The system of claim 57, wherein at least one processor circuit of the plurality of processor circuits further comprises:

a decoder circuit to decode each operational code of the plurality of operational codes to generate a corresponding plurality of control signals to control the execution circuit to perform the one or more operations corresponding to the selected operational code.

60. The system of claim 48, wherein the plurality of processor circuits further comprise:

a decoder to determine a type of description;

a parsing controller to determine or select a number of bits to parse parameter;

a stream register to store a plurality of bits of the action script; and

at least one barrel shifter to shift out of the stream register a number of bits designated by the number of bits to parse parameter.

61. The system of claim 48, wherein at least one processor circuit of the plurality of processor circuits further is to extract data from the action script and store the extracted data in the first memory circuit as a plurality of control words having corresponding data in predetermined fields.

62. The system of claim 61, wherein the at least one processor circuit of the plurality of processor circuits further is to store the plurality of operational codes and plurality of control words in a database structure.

63. The system of claim 48, wherein the plurality of descriptions are a plurality of tags, or bytecodes, or a plurality of control tags, or a plurality of definition tags, or a plurality of dictionary tags, or a plurality of dictionary repositories.

64. The system of claim 48, further comprising:

a second memory circuit storing a look up table having the plurality of operational codes; and

wherein at least one processor circuit of the plurality of processor circuits further is to perform a hash function on each description of the plurality of descriptions to generate a corresponding hash result and to use the hash result as an index or entry into the look up table to determine a corresponding operational code of the plurality of operational codes.

65. The system of claim 48, wherein at least one processor circuit of the plurality of processor circuits further comprises:

at least one arithmetic logic unit; and

at least one floating point circuit.

66. The system of claim 48, further comprising:

a configurable interconnect coupled to at least one processor circuit of the plurality of processor circuits, the configurable interconnect comprising;

a multiport register; and

a cross-point switch for configuration of a data path.

67. The system of claim 48, wherein at least one processor circuit of the plurality of processor circuits further comprises:

a post-processing circuit to match a plurality of line or curve segments of a boundary of the graphical image and to determine a sequential ordering of the plurality of line or curve segments to form boundary coordinates of the graphical image.

68. The system of claim 48, wherein at least one processor circuit of the plurality of processor circuits further comprises:

a graphics rendering circuit to apply a fill style to generate pixel data for an area of the graphical image.

69. The system of claim 68, wherein at least one processor circuit of the plurality of processor circuits further is to apply a line style by forming a second graphical image from a boundary of the graphical image, and to apply a fill style to the second graphical image to generate pixel data for the line style.

70. The system of claim 48, wherein at least one processor circuit of the plurality of processor circuits further is to perform a Transmission Control Protocol (“

TCP”

), or Internet Protocol (“

IP”

), or both TCP and IP for reception of the data.

71. The system of claim 48, wherein at least one processor circuit of the plurality of processor circuits further is to perform hypertext transfer protocol (“

HTTP”

) for reception of the data and to generate pixel data for hypertext markup language (“

HTML”

) data, or extensible markup language (“

XML”

) data, or both HTML and XML data.

72. The system of claim 71, wherein at least one processor circuit of the plurality of processor circuits further is to transfer the pixel data for the HTML or XML data to the frame buffer.

73. The system of claim 71, further comprising:

a visual display;

wherein at least one processor circuit of the plurality of processor circuits further is to transfer the pixel data for the HTML or XML data to the visual display.

74. The system of claim 71, further comprising:

a display controller;

wherein at least one processor circuit of the plurality of processor circuits further is to transfer the pixel data for the HTML or XML data to the display controller.

75. The system of claim 48, wherein the plurality of descriptions are a specification of at least one graphical image which at least partially is in a non-pixel form;

wherein each operational code of the plurality of operational codes is a hardware-level instruction or hardware-decodable into a plurality of hardware-level microcode, or hardware-level binary instructions, or hardware-level control signals;

wherein the action script is a data file which has not been fully compiled to machine code and which comprises at least one description; and

wherein the graphical image is an image of any kind for visual display which has been specified at least partially in a non-pixel form in the action script.

76. The system of claim 48, wherein at least one processor of the plurality of processors is at least one of the following:

a field programmable gate array, an application-specific integrated circuit, a microprocessor, a processor core, a cell processor, a plurality of processor cores, a digital signal processor, a reduced instruction set processor, a reconfigurable processing element, a graphics processing unit, or a computing grid.

77. A system for processing a data file for visual display of a graphical image, the data file comprising interpretable descriptions of the graphical image in a non-pixel-bitmap form, the data file not having been fully compiled to a machine code, the system comprising:

a network input and output interface to receive data;

a first memory to store data;

a frame buffer to store pixel data;

a first memory storing corresponding data; and

a plurality of processors to separate the data file from other data, to parse and convert the data file to a plurality of hardware-level operational codes and corresponding data, and to perform a plurality of operations in response to at least some hardware-level operational codes of the plurality of hardware-level operational codes to generate pixel data for the graphical image.

78. The system of claim 77, wherein a first processor of the plurality of processors further is to parse the data file into a plurality of descriptive elements and corresponding data, wherein the first processor or a second processor of the plurality of processors is to convert at least some descriptive elements of the plurality of descriptive elements into the plurality of hardware-level operational codes and corresponding data, and the second processor or a third processor of the plurality of processors is to perform at least one operation, of the plurality of operations, corresponding to a hardware-level operational code of the plurality of hardware-level operational codes using corresponding data to generate pixel data for the graphical image.

79. The system of claim 78, wherein at least one processor of the plurality of processors further is to decode at least some of the data file to determine a corresponding parsing operational code of the plurality of hardware-level operational codes to control the parsing of the data file.

80. The system of claim 77, wherein at least one processor of the plurality of processors further is to extract data from the data file and store the extracted data in the first memory as a plurality of control words having corresponding data in predetermined fields.

81. The system of claim 77, wherein at least one processor of the plurality of processors is at least one of the following:

a field programmable gate array, an application-specific integrated circuit, a microprocessor, a processor core, a cell processor, a plurality of processor cores, a digital signal processor, a reduced instruction set processor, a reconfigurable processing element, a graphics processing unit, or a computing grid.

82. The system of claim 77, further comprising:

a second memory to store a look up table having the plurality of hardware-level operational codes; and

wherein at least one processor of the plurality of processors further is to convert the parsed data file directly to the plurality of hardware-level operational codes by performing a hash function on each descriptive element of a plurality of descriptive elements to generate a corresponding hash result and to use the hash result as an index or entry into the look up table to determine a corresponding hardware-level operational code of the plurality of hardware-level operational codes.

83. A system for processing a data file for visual display of a graphical image, the data file comprising at least one description of the graphical image in a non-pixel-bitmap form, the data file further comprising data which is not fully compiled to executable machine code, the system comprising:

a network input and output interface to receive the data file;

a first memory;

first circuitry to convert a plurality of descriptive elements of the data file into a plurality of operational codes;

second circuitry to perform one or more operations corresponding to an operational code of the plurality of operational codes to generate pixel data for the graphical image; and

a frame buffer to store the pixel data.

84. The system of claim 83, further comprising:

a display controller coupled to the frame buffer to receive the pixel data; and

a display coupled to the display controller, the display to visually display the graphical image.

85. The system of claim 83, further comprising:

third circuitry to parse the data file into the plurality of descriptive elements and corresponding data.

86. The system of claim 85, further comprising:

fourth circuitry to decode a descriptive element to determine a corresponding parsing operational code of the plurality of operational codes to control the parsing of the data file.

87. The system of claim 85, wherein the third circuitry further comprises:

a decoder to determine a type of descriptive element;

a parsing controller to determine or select a number of bits to parse parameter;

a stream register to store a plurality of bits of the action script; and

at least one barrel shifter to shift out of the stream register a number of bits designated by the number of bits to parse parameter.

88. The system of claim 83, further comprising:

fifth circuitry to extract data from the data file and to store the extracted data in the first memory as a plurality of control words having corresponding data in predetermined fields.

89. The system of claim 88, wherein each control word of the plurality of control words comprises:

a starting or an ending x-coordinate and y-coordinate for a corresponding line or curve segment for the graphical image;

a first memory address for line style array for a corresponding line or curve segment for the graphical image; and

a second memory address for fill style array for a plurality of line or curve segments comprising the graphical image.

90. The system of claim 83, further comprising:

sixth circuitry to decode each operational code of the plurality of operational codes to generate a corresponding plurality of control signals to control the second circuitry to perform a selected operation, of a plurality of operations, corresponding to a selected operational code of the plurality of operational codes.

91. The system of claim 83, further comprising:

a configurable interconnect coupled to the first circuitry and the second circuitry, the configurable interconnect comprising;

a multiport register; and

a cross-point switch for configuration of a data path.

92. The system of claim 83, further comprising:

seventh circuitry to match a plurality of line or curve segments of a boundary of the graphical image and to determine a sequential ordering of the plurality of line or curve segments to form boundary coordinates of the graphical image.

93. The system of claim 83, further comprising:

eighth circuitry to separate the data file from other received data;

ninth circuitry to perform hypertext transfer protocol (“

HTTP”

); and

tenth circuitry to generate pixel data for hypertext markup language (“

HTML”

) data, or extensible markup language (“

XML”

) data, or both HTML and XML data of the data file.

94. The system of claim 93, wherein the first circuitry, the second circuitry, the eighth circuitry, the ninth circuitry, and the tenth circuitry are embodied in a single integrated circuit.

95. The system of claim 93, wherein the first circuitry, the second circuitry, the eighth circuitry, the ninth circuitry, and the tenth circuitry further comprise at least one of the following:

a field programmable gate array, an application-specific integrated circuit, a microprocessor, a processor core, a cell processor, a plurality of processor cores, a digital signal processor, a reduced instruction set processor, a reconfigurable processing element, a graphics processing unit, or a computing grid.