MEMORY DEVICE AND MANUFACTURING METHOD THE SAME

• US 20100149851A1
• Filed: 02/24/2010
• Published: 06/17/2010
• Est. Priority Date: 03/28/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, SAKAKURA, Masayuki, TAKANO, Tamae, NOMURA, Ryoji, ASAMI, Yoshinobu
• Granted Patent: US 8,238,152 B2
• Time in Patent Office: Days
• US Class Current: 365/72
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/34 using semiconductor devices
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 23/4828 Conductive organic material or pastes, e.g. conductive adhesives, inks
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/33 the capacitor extending under the transistor
• CPC Class Codes: H10K 19/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
• CPC Class Codes: H10K 19/80 Interconnections, e.g. terminals

Abstract

A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element.

Claims

1. A semiconductor device comprising:

a bit line driver circuit including a column decoder and a read circuit;

a word line driver circuit including a row decoder; and

a memory cell including a first wiring, a second wiring, and a transistor, the transistor having a semiconductor film including a channel formation region,

wherein the first wiring is electrically connected to the bit line driver circuit,

wherein the second wiring is electrically connected to the word line driver circuit, and

wherein the semiconductor film includes a metal oxide and the metal includes indium.

2. The semiconductor device according to claim 1,

wherein the memory cell further comprises a first conductive layer electrically connected to the transistor, a layer including an organic compound, and a second conductive layer,

wherein the first conductive layer is overlapped with the second conductive layer, and

wherein the layer including the organic compound is interposed between the first conductive layer and the second conductive layer.

3. The semiconductor device according to claim 1,

wherein the word line driver circuit further comprises a level shifter.

4. The semiconductor device according to claim 1, wherein the transistor is any one of a top gate transistor, a bottom gate transistor, and a forward stagger transistor.

5. The semiconductor device according to claim 1,

wherein the metal oxide is In—

Ga—

Zn—

O.

6. A semiconductor device comprising:

a bit line driver circuit including a column decoder and a read circuit;

a word line driver circuit including a row decoder; and

a memory cell including a first wiring, a second wiring, a first transistor, and a second transistor, at least one of the first transistor and the second transistor having a semiconductor film including a channel formation region,

wherein the first wiring is electrically connected to the bit line driver circuit,

wherein the second wiring is electrically connected to the word line driver circuit, and

wherein the semiconductor film includes a metal oxide and the metal includes indium.

7. The semiconductor device according to claim 6,

wherein the memory cell further comprises a first conductive layer electrically connected to the first transistor, a layer including an organic compound, and a second conductive layer,

wherein the first conductive layer is overlapped with the second conductive layer, and

wherein the layer including the organic compound is interposed between the first conductive layer and the second conductive layer.

8. The semiconductor device according to claim 6,

wherein the word line driver circuit further comprises a level shifter.

9. The semiconductor device according to claim 6, wherein the first transistor and the second transistor are any one of a top gate transistor, a bottom gate transistor, and a forward stagger transistor.

10. The semiconductor device according to claim 6,

wherein the metal oxide is In—

Ga—

Zn—

O.

11. The semiconductor device according to claim 6,

wherein both of the first transistor and the second transistor have the semiconductor film.

12. A semiconductor device comprising:

an integrated circuit including a memory, the memory comprising;

a bit line driver circuit including a column decoder and a read circuit;

a word line driver circuit including a row decoder; and

a memory cell including a first wiring, a second wiring, and a transistor, the transistor having a semiconductor film including a channel formation region; and

an antenna electrically connected to the integrated circuit,

wherein the first wiring is electrically connected to the bit line driver circuit,

wherein the second wiring is electrically connected to the word line driver circuit, and

wherein the semiconductor film includes a metal oxide and the metal includes indium.

13. The semiconductor device according to claim 12,

wherein the memory cell further comprises a first conductive layer electrically connected to the transistor, a layer including an organic compound, and a second conductive layer,

wherein the first conductive layer is overlapped with the second conductive layer, and

wherein the layer including the organic compound is interposed between the first conductive layer and the second conductive layer.

14. The semiconductor device according to claim 12,

wherein the word line driver circuit further comprises a level shifter.

15. The semiconductor device according to claim 12, wherein the transistor is any one of a top gate transistor, a bottom gate transistor, and a forward stagger transistor.

16. The semiconductor device according to claim 12,

wherein the metal oxide is In—

Ga—

Zn—

O.

17. A semiconductor device comprising:

an integrated circuit including a memory, the memory comprising;

a bit line driver circuit including a column decoder and a read circuit;

a word line driver circuit including a row decoder; and

a memory cell including a first wiring, a second wiring, a first transistor, and a second transistor, at least one of the first transistor and the second transistor having a semiconductor film including a channel formation region; and

an antenna electrically connected to the integrated circuit,

wherein the first wiring is electrically connected to the bit line driver circuit,

wherein the second wiring is electrically connected to the word line driver circuit, and

wherein the semiconductor film includes a metal oxide and the metal includes indium.

18. The semiconductor device according to claim 17,

wherein the memory cell further comprises a first conductive layer electrically connected to the first transistor, a layer including an organic compound, and a second conductive layer,

wherein the first conductive layer is overlapped with the second conductive layer, and

wherein the layer including the organic compound is interposed between the first conductive layer and the second conductive layer.

19. The semiconductor device according to claim 17,

wherein the word line driver circuit further comprises a level shifter.

20. The semiconductor device according to claim 17, wherein the first transistor and the second transistor are any one of a top gate transistor, a bottom gate transistor, and a forward stagger transistor.

21. The semiconductor device according to claim 17,

wherein the metal oxide is In—

Ga—

Zn—

O.

22. The semiconductor device according to claim 17,

wherein both of the first transistor and the second transistor have the semiconductor film.

23. A semiconductor device comprising:

an integrated circuit including a power source circuit, a clock generator circuit, a control circuit and a memory, the memory comprising;

a bit line driver circuit including a column decoder and a read circuit;

a word line driver circuit including a row decoder; and

a memory cell including a first wiring, a second wiring, and a transistor, the transistor having a semiconductor film including a channel formation region; and

an antenna electrically connected to the integrated circuit,

wherein the first wiring is electrically connected to the bit line driver circuit,

wherein the second wiring is electrically connected to the word line driver circuit, and

wherein the semiconductor film including a metal oxide and the metal includes indium.

24. The semiconductor device according to claim 23,

wherein the memory cell further comprises a first conductive layer electrically connected to the transistor, a layer including an organic compound, and a second conductive layer,

wherein the first conductive layer is overlapped with the second conductive layer, and

wherein the layer including the organic compound is interposed between the first conductive layer and the second conductive layer.

25. The semiconductor device according to claim 23,

wherein the word line driver circuit further comprises a level shifter.

26. The semiconductor device according to claim 23, wherein the transistor is any one of a top gate transistor, a bottom gate transistor and a forward stagger transistor.

27. The semiconductor device according to claim 23,

wherein the metal oxide is In—

Ga—

Zn—

O.

28. The semiconductor device according to claim 23, wherein the integrated circuit further comprises a data demodulation/modulation circuit, an interface circuit, and a data bus.

29. A semiconductor device comprising:

an integrated circuit including a power source circuit, a clock generator circuit, a control circuit and a memory, the memory comprising;

a bit line driver circuit including a column decoder and a read circuit;

a word line driver circuit including a row decoder; and

a memory cell including a first wiring, a second wiring, a first transistor, and a second transistor, at least one of the first transistor and the second transistor having a semiconductor film including a channel formation region; and

an antenna electrically connected to the integrated circuit,

wherein the first wiring is electrically connected to the bit line driver circuit,

wherein the second wiring is electrically connected to the word line driver circuit, and

wherein the semiconductor film includes a metal oxide and the metal includes indium.

30. The semiconductor device according to claim 29,

wherein the memory cell further comprises a first conductive layer electrically connected to the first transistor, a layer including an organic compound, and a second conductive layer,

wherein the first conductive layer is overlapped with the second conductive layer, and

wherein the layer including the organic compound is interposed between the first conductive layer and the second conductive layer.

31. The semiconductor device according to claim 29,

wherein the word line driver circuit further comprises a level shifter.

32. The semiconductor device according to claim 29, wherein the first transistor and the second transistor are any one of a top gate transistor, a bottom gate transistor, and a forward stagger transistor.

33. The semiconductor device according to claim 29,

wherein the metal oxide is In—

Ga—

Zn—

O.

34. The semiconductor device according to claim 29, wherein the integrated circuit further comprises a data demodulation/modulation circuit, an interface circuit, and a data bus.

35. The semiconductor device according to claim 29,

wherein both of the first transistor and the second transistor have the semiconductor film.