NON-VOLATILE SEMICONDUCTOR MEMORY, AND THE METHOD THEREOF

• US 20100149870A1
• Filed: 12/03/2009
• Published: 06/17/2010
• Est. Priority Date: 12/04/2008
• Status: Active Grant

• Current Assignee: Powerchip Semiconductor Manufacturing Corp. (Powerchip Technology Corporation)
• Original Assignee: Powerchip Technology Corporation
• Inventors: SHIROTA, Riichiro
• Granted Patent: US 8,223,541 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A non-volatile semiconductor memory and a writing method thereof are provided for preventing miswriting induced by gate-induced-drain leakage (GIDL). The non-volatile semiconductor memory comprises a non-volatile memory cell array 10 for recording multiple values by setting a plurality of different thresholds to each memory cell transistor that is connected in series between selection transistors Qs1 and Qs2 on two terminals of a selected bit line; and a control circuit 11 for controlling writing of the data from the memory cell array 10. The control circuit 11 records two values for at least a plurality of first memory cell transistors Q0, Q1, Q32 and Q33 respectively adjacent to the selection transistors Qs1 and Qs2 on two terminals of the bit line, and records more than three values for a plurality of second transistors Q2˜Q31 other than the first memory cell transistors.

Claims

1. A non-volatile semiconductor memory device, comprising:

a non-volatile memory cell array for recording multiple values by setting a plurality of different threshold voltages to each memory cell transistor, wherein each memory cell transistor is connected in series between selection transistors on two terminals of a selected bit line; and

a control circuit for controlling programmed data of the memory cell array,

wherein the control circuit records two values for at least a plurality of first memory cell transistors respectively adjacent to the selection transistors on the two terminals, and records more than three multiple values for a plurality of second transistors other than the first memory cell transistors.

2. The non-volatile semiconductor memory device as claimed in claim 1, wherein the control circuit records the two values for two of the first memory cell transistors respectively adjacent to the selection transistors on the two terminals.

3. The non-volatile semiconductor memory device as claimed in claim 2, wherein the control circuit divides the data into a predetermined number and writes the data into each page of the first memory cell transistors recorded by the two values for recording the data.

4. The non-volatile semiconductor memory device as claimed in claim 1, wherein the control circuit sets a programming/verifying voltage of the first memory cell transistors recorded by the two values to a voltage which is lower than a verifying voltage for recording the data, and wherein the verifying voltage for recording the data has a maximum threshold voltage level for a plurality of recorded data recorded by the multiple values.

5. The non-volatile semiconductor memory device as claimed in claim 1, wherein the control circuit sets a programming/verifying voltage of the first memory cell transistors recorded by the two values to a voltage which is lower than a verifying voltage for recording the data, and wherein the verifying voltage for recording the data has a low threshold voltage level which is lower than a maximum threshold voltage level for a plurality of recorded data recorded by the multiple values.

6. A write-in method for a non-volatile semiconductor memory device, wherein the non-volatile semiconductor memory device comprises a non-volatile memory cell array and a control circuit, the memory cell array records multiple values by setting a plurality of different threshold voltages to each memory cell transistor, each memory cell transistor is coupled in series between the selection transistors on two terminals of a selected bit line, and the control circuit controls programmed data of the memory cell array, comprising:

a control step for recording two values for at least a plurality of first memory cell transistors respectively adjacent to the selection transistors on the two terminals, and recording more than three multiple values for a plurality of second transistors other than the first memory cell transistors.

7. The write-in method as claimed in claim 6, wherein the control step further comprises the step of:

recording the two values for two of the first memory cell transistors respectively adjacent to the selection transistors on the two terminals.

8. The write-in method as claimed in claim 6, wherein the control step further comprises the step of:

dividing the data into a predetermined number and writing the data into each page of the first memory cell transistors recorded by the two values for recording the data.

9. The write-in method as claimed in claim 6, wherein the control step further comprises the step of:

setting a programming/verifying voltage of the first memory cell transistors recorded by the two values to a voltage which is lower than a verifying voltage for recording the data, and wherein the verifying voltage for recording the data has a maximum threshold voltage level for a plurality of recorded data recorded by the multiple values.

10. The write-in method as claimed in claim 6, wherein the control step further comprises the step of:

setting the programming/verifying voltage of the first memory cell transistors recorded by the two values to a voltage which is lower than a verifying voltage for recording data, and wherein the verifying voltage for recording the data has a low threshold voltage level which is lower than a maximum threshold voltage level for a plurality of recorded data recorded by the multiple values.