REDUCTION OF POWER CONSUMPTION IN A MEMORY DEVICE DURING SLEEP MODE OF OPERATION

• US 20100149884A1
• Filed: 11/11/2009
• Published: 06/17/2010
• Est. Priority Date: 11/11/2008
• Status: Abandoned Application

• Current Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: Kumar, Ashish
• Application Number:
  US12/616,296
• Publication Number:
  US 20100149884A1
• Time in Patent Office: Days
• US Class Current: 365/189.90
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

The present disclosure relates to a system comprising memory device with a power switch where the system comprises a first voltage controlled switch coupling positive power supply to positive supply terminal of memory device core; a second voltage controlled switch coupling negative power supply to negative supply terminal of the memory device core; a first reference voltage coupled to the substrate terminal of said first voltage controlled switch; and a second reference voltage coupled to the substrate terminal of said second voltage controlled switch. This helps maintain a sufficient RNM for efficient performance by the system.

Claims

1. A system comprising a memory device with a bias generation unit, said system comprising:

—

a first voltage controlled switch coupling positive power supply to positive supply terminal of memory device core;

a second voltage controlled switch coupling negative power supply to negative supply terminal of the memory device core;

a first reference voltage coupled to the substrate terminal of said first voltage controlled switch; and

a second reference voltage coupled to the substrate terminal of said second voltage controlled switch.

2. The system as claimed in claim 1 wherein the first voltage controlled switch comprises a first forward biased diode in parallel with a P channel MOS transistor.

3. The system as claimed in claim 1 wherein the second voltage controlled switch comprises a second forward biased diode in parallel with an N channel MOS transistor.

4. The system as claimed in claim 1 wherein the first and second reference voltages are functions of threshold voltage of the first and second voltage controlled switch respectively.

5. A memory device comprising a bias generation unit, said memory device comprising:

—

a first voltage controlled switch coupling positive power supply to positive supply terminal of memory device core;

a second voltage controlled switch coupling negative power supply to negative supply terminal of the memory device core;

a first reference voltage coupled to the substrate terminal of said first voltage controlled switch; and

a second reference voltage coupled to the substrate terminal of said second voltage controlled switch.

6. The memory device as claimed in claim 5 wherein the first voltage controlled switch comprises a first forward biased diode in parallel with a P channel MOS transistor.

7. The memory device as claimed in claim 5 wherein the second voltage controlled switch comprises a second forward biased diode in parallel with an N channel MOS transistor.

8. The memory device as claimed in claim 5 wherein the first and second reference voltages are functions of threshold voltage of the first and second voltage controlled switch respectively.

9. A method of reducing power consumption in a memory device during sleep mode of operation comprising the steps of:

—

biasing substrate terminal of a first voltage controlled switch to a first reference voltage; and

biasing substrate terminal of a second voltage controlled switch to a second reference voltage.

10. A method as claimed in claim 9 wherein the first and second reference voltages are functions of threshold voltage of the first and second voltage controlled switches respectively.