SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING POWER SOURCE
First Claim
1. A semiconductor memory device comprising a writing margin monitoring circuit, the writing margin monitoring circuit comprising a simulation circuit in which a replicated load transistor and a replicated access transistor are connected in series, the replicated load transistor and the replicated access transistor respectively simulating a load transistor and an access transistor of a SRAM cell so that a current flowing to the access transistor that discharges a potential of a storage node of the SRAM cell equals a current flowing to the load transistor of the SRAM cell at a writing operation.
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Accused Products
Abstract
A voltage generator that monitors a writing margin as a control amount in order to carry out an optimum power source control when control of a SRAM cell power source is carried out at writing operation, and always keeps the writing margin constant; and a power source selector are included to switch power source voltage at writing. By switching the power source voltage at writing, a semiconductor memory device in which a stable writing operation is achieved without largely deteriorating writing time in the SRAM cell and an ultrahigh speed operation or ultralow power operation can be carried out is obtained.
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Citations
14 Claims
- 1. A semiconductor memory device comprising a writing margin monitoring circuit, the writing margin monitoring circuit comprising a simulation circuit in which a replicated load transistor and a replicated access transistor are connected in series, the replicated load transistor and the replicated access transistor respectively simulating a load transistor and an access transistor of a SRAM cell so that a current flowing to the access transistor that discharges a potential of a storage node of the SRAM cell equals a current flowing to the load transistor of the SRAM cell at a writing operation.
- 13. A method of controlling a power source of a semiconductor memory device, the semiconductor memory device comprising a simulation circuit, a replicated inverter circuit, an operational amplifier, a voltage generator and a power source selector, the simulation circuit being constructed from a replicated load transistor and a replicated access transistor that respectively simulate a load transistor and an access transistor that configure a SRAM cell, the replicated inverter circuit being constructed from second replicated load transistor and replicated drive transistor to which an output from the simulation circuit is inputted, outputs from the simulation circuit and the replicated inverter circuit being inputted to the operational amplifier, the voltage generator generating second high power source voltage or second low power source voltage by means of an output from the operational amplifier, wherein when a writing instruction is inputted, the power source selector applies either the second high power source voltage and low power source voltage or high power source voltage and the second low power source voltage as a power source of the SRAM cell.
Specification