Group III-V semiconductor device and method for producing the same

• US 20100151612A1
• Filed: 02/22/2010
• Published: 06/17/2010
• Est. Priority Date: 03/16/2007
• Status: Active Grant

• Current Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Original Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Inventors: Ando, Masanobu, Tomita, Kazuyoshi, Kinoshita, Yoshinori, Horiuchi, Shigemi
• Granted Patent: US 8,420,502 B2
• Time in Patent Office: Days
• US Class Current: 438/46
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/025 Physical imperfections, e.g. particular concentration or distribution of impurities
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector

Abstract

A method for producing a Group III-V semiconductor device, includes forming, on a base, a plurality of semiconductor devices isolated from one another, forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device, after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device, bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer, and removing the base through the laser lift-off process.

Claims

1. A method for producing a Group III-V semiconductor device, the method comprising:

forming, on a base, a plurality of semiconductor devices isolated from one another;

forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device;

after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device;

bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and

removing the base through the laser lift-off process.

2. A semiconductor device production method as described in claim 1, wherein the side surface of the semiconductor device is formed to be inclined so that the device has a cross-sectional area gradually increasing toward the base, and ion implantation is performed along a direction normal to the main plane of the base.

3. A semiconductor device production method as described in claim 1, wherein ion implantation is performed along a direction normal to the main plane of the base at an acceleration voltage which allows the implanted ions to reach the base.

4. A semiconductor device production method as described in claim 1, which includes, after removal of the base, performing ion implantation into a portion of the surface of the semiconductor device which surface has previously bonded to the base, the portion is in the vicinity of the side surface.

5. A semiconductor device production method as described in claim 1, which includes, after removal of the base, forming an n-electrode on the surface of the semiconductor device which surface has previously bonded to the base, and performing ion implantation into the surface of the semiconductor device through the n-electrode, which serves as a mask.

6. A semiconductor device production method as described in claim 1, which includes, after removal of the base, forming a dielectric material insulating film on a portion of the surface of the semiconductor device which surface has previously bonded to the base, the portion being in the vicinity of the side surface.

8. A semiconductor device production method as described in claim 3, wherein ion implantation is performed at a plurality of times at different acceleration voltages.

10. A semiconductor device production method as described in claim 1, wherein the low-melting-point metal layer comprises at least one selected from a group consisting of Au—

Sn, Au—

Si, Ag—

Sn—

Cu, and Sn—

Bi.

11. A semiconductor device production method as described in claim 1, wherein the semiconductor device comprises a Group III nitride semiconductor device.

12. A semiconductor device production method as described in claim 1, wherein the semiconductor device comprises a light-emitting device.

7. A method for producing a Group III-V semiconductor device, the method comprising:

forming a Group III-V semiconductor layer on a base;

forming a high-resistance region in a surface layer of a predetermined portion of the top surface of the semiconductor layer through ion implantation at an acceleration voltage which allows the implanted ions to reach the base;

dividing the semiconductor layer, through the high-resistance region, into semiconductor devices isolated from one another;

after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of each semiconductor device;

bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and

removing the base through the laser lift-off process.

9. A method for producing a Group III-V semiconductor device, the method comprising:

forming a Group III-V semiconductor layer on a base;

forming a first high-resistance region in a surface layer of a predetermined portion of the top surface of the semiconductor layer through ion implantation at an acceleration voltage which does not allow the implanted ions to reach the base;

after formation of the first high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor layer;

bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer;

removing the base through the laser lift-off process; and

forming, in addition to the first high-resistance region, a second high-resistance region in a surface layer of a predetermined portion of the surface of the semiconductor layer which surface has previously bonded to the base, the portion corresponding to the first high-resistance region, through ion implantation at an acceleration voltage which allows the implanted ions to reach the first high-resistance region; and

dividing the semiconductor layer, through the first and second high-resistance regions, into semiconductor devices isolated from one another.