DMA (DIRECT MEMORY ACCESS) COALESCING

• US 20100153590A1
• Filed: 12/29/2009
• Published: 06/17/2010
• Est. Priority Date: 09/17/2007
• Status: Active Grant

• Current Assignee: Chih-Fan Hsin, Jr-Shian Tsai, Tsung-Yuan C. Tai
• Original Assignee: Intel Corporation
• Inventors: Hsin, Chih-Fan, Tai, Tsung-Yuan C., Tsai, Jr-Shian
• Granted Patent: US 8,661,167 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

In general, in one aspect, a method includes determining a repeated, periodic DMA (Direct Memory Access) coalescing interval based, at least in part, on a power sleep state of a host platform. The method also includes buffering data received at the device in a FIFO (First-In-First-Out) queue during the interval and DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.

Claims

1. A method comprising, at a device having at least one Direct Memory Access (DMA) engine:

determining a repeated, periodic DMA coalescing interval based, at least in part, on a power sleep state of a host platform;

buffering data received at the device in a FIFO (First-In-First-Out) queue during the repeated, periodic DMA coalescing interval; and

DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.

2. The method of claim 1, wherein the device comprises a network interface controller comprising at least one PHY and at least one MAC (media access controller).

3. The method of claim 1, further comprising:

disabling DMA coalescing based on a first determined rate of data; and

resuming DMA coalescing based on a second determined rate of data.

4. The method of claim 1, further comprising:

detecting at least one characteristic of a packet received by the device based on at least one packet header field; and

based on the detecting the at least one characteristic, DMA-ing at least the packet prior to expiration of the repeated, periodic DMA coalescing interval.

5. The method of claim 1, further comprising:

determining timing of at least one interrupt generated by the device based on the repeated, periodic DMA coalescing interval.

6. The method of claim 1, wherein the timing of the at least one interrupt comprises a first interrupt based on an end of a first DMA coalescing interval.

7. The method of claim 1, further comprising:

receiving a signal from a host processor sent to multiple coupled devices; and

in response, terminating a DMA coalescing interval prematurely.

8. The method of claim 1, wherein the determining comprises repeatedly dynamically adjusting the DMA coalescing interval during continuing operation.

9. The method of claim 1, further comprising:

comparing buffer occupancy with a threshold; and

based on the comparing, terminating DMA coalescing prior to the expiration of the repeated, periodic DMA coalescing interval.

10. A network interface controller comprising:

at least one PHY;

at least one MAC (media access controller) communicatively coupled to the at least one PHY;

at least at least one Direct Memory Access (DMA) engine to transfer packets received via the at least on PHY and at least one MAC to a host memory;

logic to;

determine a repeated, periodic DMA coalescing interval based, at least in part, on a power sleep state of a host platform;

buffer data received at the device in a FIFO (First-In-First-Out) queue during the repeated, periodic DMA coalescing interval; and

DMA the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.

11. The network interface controller of claim 10, further comprising logic to:

disable DMA coalescing based on a first determined rate of data; and

resume DMA coalescing based on a second determined rate of data.

12. The network interface controller of claim 10, further comprising logic to:

detect at least one characteristic of a packet received by the device based on at least one packet header field; and

based on the detecting the at least one characteristic, DMA at least the packet prior to expiration of the repeated, periodic DMA coalescing interval.

13. The network interface controller of claim 10, further comprising logic to:

determine timing of at least one interrupt generated by the device based on the repeated, periodic DMA coalescing interval.

14. The network interface controller of claim 10, wherein the timing of the at least one interrupt comprises a first interrupt based on an end of a first DMA coalescing interval.

15. The network interface controller of claim 10, further comprising logic to:

receive a signal sent to multiple coupled devices; and

in response, terminating a DMA coalescing interval prematurely.

16. The network interface controller of claim 15, wherein the logic to determine comprises logic to repeatedly, dynamically adjust the DMA coalescing interval during continuing operation.

17. The network interface controller of claim 10, further comprising logic to:

compare buffer occupancy with a threshold; and

based on the comparing, terminate DMA coalescing prior to the expiration of the repeated, periodic DMA coalescing interval.

18. A method, comprising:

sending at least one signal to multiple devices coupled to a host platform to control DMA coalescing of the multiple devices;

wherein DMA coalescing comprises buffering data to DMA to host platform memory during a respective DMA coalescing duration of the respective multiple devices.

19. The method of claim 18,

wherein the sending at least one signal comprises sending a signal terminating an on-going DMA coalescing duration at at least some of the multiple devices.

20. The method of claim 18,

wherein the sending at least one signal comprises sending from a single device driver.

21. The method of claim 18,

wherein the sending at least signal comprises sending data descriptive of a DMA coalescing configuration for a one of the respective devices.