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METHODS AND SYSTEMS TO ALLOCATE ADDRESSES IN A HIGH-ENDURANCE/LOW-ENDURANCE HYBRID FLASH MEMORY

  • US 20100153616A1
  • Filed: 12/16/2008
  • Published: 06/17/2010
  • Est. Priority Date: 12/16/2008
  • Status: Active Grant
First Claim
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1. A system, comprising:

  • memory, including first and second types of electrically erasable programmable random access memory cells, configured to be erased in blocks of memory cells, wherein the first type of memory cells has a greater erase-endurance than the second type of memory cells; and

    a memory controller to selectively map higher-usage logical addresses to the first type of memory cells and lower-usage logical addresses to the second type of memory cells.

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