METHODS AND SYSTEMS TO ALLOCATE ADDRESSES IN A HIGH-ENDURANCE/LOW-ENDURANCE HYBRID FLASH MEMORY

• US 20100153616A1
• Filed: 12/16/2008
• Published: 06/17/2010
• Est. Priority Date: 12/16/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Garratt, Jason
• Granted Patent: US 8,209,466 B2
• Time in Patent Office: Days
• US Class Current: 711/6
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

Methods and systems to selectively map higher-usage addresses to higher-endurance memory cells of a flash memory, and lower-usage addresses to lower-endurance memory cells of the flash memory. Address usage may be determined with respect to the most recent write operation corresponding to an address and/or with respect to a frequency of write operations corresponding to the address. Higher-endurance memory cells may include single level cells (SLCs). Lower-endurance memory cells may include multi-level cells (MLCs). Improved endurance may be obtained with a relatively small percentage of higher-endurance memory cells, at a relatively low cost.

Claims

1. A system, comprising:

memory, including first and second types of electrically erasable programmable random access memory cells, configured to be erased in blocks of memory cells, wherein the first type of memory cells has a greater erase-endurance than the second type of memory cells; and

a memory controller to selectively map higher-usage logical addresses to the first type of memory cells and lower-usage logical addresses to the second type of memory cells.

2. The system according to claim 1, wherein the first type of memory cells includes single-bit-per-cell memory cells and the second type of memory cells include multiple-bits-per-cell memory cells.

3. The system according to claim 2, wherein the second type of memory cells includes three-bits-per-cell memory cells.

4. The system according to claim 2, wherein the first type of memory cells accounts for less than ten percent of a storage capacity of the memory.

5. The system according to claim 1, wherein the memory controller includes a microcontroller and a computer program product including a computer readable medium having computer program logic stored therein, the computer program logic including:

map logic to cause the microcontroller to map more recently accessed logical addresses to the first type of memory cells and less recently accessed logical addresses to the second type of memory cells.

6. The system according to claim 5, wherein the map logic includes:

count logic to cause the microcontroller to increment a count upon each write request;

association logic to cause the microcontroller to associate a current value of the count with a logical address upon a write operation corresponding to the logical address; and

selection logic to cause the microcontroller to map a logical address to the first type of memory cells when the count value associated with the logical address is greater than a threshold, and to map the logical address to the second type of memory cells when the count value associated with the logical address is less than the threshold.

7. The system according to claim 6, wherein the map logic further includes:

re-map logic to cause the microcontroller to re-map a portion of the logical addresses from the first type of memory cells to the second type of memory cells when the first type of memory cells is substantially near a storage capacity; and

threshold logic to cause the microcontroller to set the threshold to a lowest count value of a logical address that remains mapped to the first type of memory cells following a re-map.

8. The system according to claim 1, wherein the memory controller includes a microcontroller and a computer program product including a computer readable medium having computer program logic stored therein, the computer program logic including:

map logic to cause the microcontroller to map more frequently accessed logical addresses to the first type of memory cells and less frequently accessed logical addresses to the second type of memory cells.

9. The system according to claim 1, further comprising:

a computer system including an instruction processor circuit board; and

a communication interface between the instruction processor circuit board and the memory;

wherein the instruction processor circuit board is configured to access the memory as system memory.

10. The system according to claim 9, wherein the instruction processor circuit board includes at least a portion of the memory controller.

11. A method, comprising:

receiving write requests including data and corresponding logical memory addresses; and

writing the data to a flash memory including first and second types of memory cells, wherein the first type of memory cells has a greater erase-endurance than the second type of memory cells;

wherein the writing includes selectively mapping higher-usage logical addresses to the first type of memory cells and lower-usage logical addresses to the second type of memory cells.

12. The method according to claim 11, wherein the selectively mapping includes:

mapping relatively high-usage logical addresses to single-bit-per-cell memory cells; and

mapping relatively low-usage logical addresses to multiple-bits-per-cell memory cells.

13. The method according to claim 12, wherein the selectively mapping further includes:

mapping relatively low-usage logical addresses to three-bits-per-cell memory cells.

14. The method according to claim 11, wherein the selectively mapping includes:

mapping more recently accessed logical addresses to the first type of memory cells; and

mapping less recently accessed logical addresses to the second type of memory cells.

15. The method according to claim 14, further comprising:

incrementing a count upon each write request; and

associating a current value of the count with a logical address upon a write corresponding to the logical address;

wherein the selectively mapping includes mapping a logical address to the first type of memory cells when the count value associated with the logical address is greater than a threshold value, and mapping the logical address to the second type of memory cells when the count value associated with the logical address is less than the threshold value.

16. The method according to claim 15, further comprising:

re-mapping a portion of the logical addresses from the first type of memory cells to the second type of memory cells when the first type of memory cells is substantially near a storage capacity; and

setting the threshold value to a lowest count value of a logical address that remains mapped to the first type of memory cells following the re-mapping.

17. The method according to claim 11, wherein the selectively mapping includes:

mapping more frequently accessed logical addresses to the first type of memory cells; and

mapping less frequently accessed logical addresses to the second type of memory cells.

18. A computer program product including a computer readable medium having computer program logic stored therein, the computer program logic including:

memory access logic to cause a processor to control access to a flash memory having first and second types of electrically erasable programmable random access memory cells configured to be erased in blocks of memory cells, wherein the first type of memory cells has a greater erase-endurance than the second type of memory cells; and

map logic to cause the processor to selectively map higher-usage logical addresses to the first type of memory cells and lower-usage logical addresses to the second type of memory cells.

19. The computer program product of claim 18, wherein the map logic includes:

count logic to cause the processor to increment a count upon each write request;

association logic to cause the processor to associate a current value of the count with a logical address upon a write operation corresponding to the logical address; and

selection logic to cause the processor to map a logical address to the first type of memory cells when the count value associated with the logical address is greater than a threshold, and to map the logical address to the second type of memory cells when the count value associated with the logical address is less than the threshold.

20. The computer program product of claim 19, wherein the map logic further includes:

re-map logic to cause the processor to re-map a portion of the logical addresses from the first type of memory cells to the second type of memory cells when the first type of memory cells is substantially near a storage capacity; and

threshold logic to cause the processor to set the threshold value to a lowest count value of a logical address that remains mapped to the first type of memory cells following a re-map.