NON-VOLATILE MEMORY SYSTEM STORING DATA IN SINGLE-LEVEL CELL OR MULTI-LEVEL CELL ACCORDING TO DATA CHARACTERISTICS

• US 20100153632A1
• Filed: 02/24/2010
• Published: 06/17/2010
• Est. Priority Date: 11/03/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Chan-ik, TALAWAR, Prakash, LEE, Yang-sup
• Granted Patent: US 8,214,582 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Provided is a system storing data received from an application or file system in a non-volatile memory system of single-level cells and multi-level cells in accordance with one or more data characteristics. The non-volatile memory system includes a non-volatile memory cell array having a plurality of multi-level cells forming a MLC area and a plurality of single-level cells forming a SLC area, and an interface unit analyzing a characteristic of the write data and generating a corresponding data characteristic signal. A flash transition layer receives the data characteristic signal, and determines whether the write data should be stored in the MLC area or the SLC area based on whether or not the write data will be accessed by the file, or whether the address associated with the write data is frequently updated or not.

Claims

1. The non-volatile memory system comprises:

a non-volatile memory cell array having a plurality of multi-level cells forming a MLC area and a plurality of single-level cells forming a SLC area; and

a flash transition layer receiving the write data from the at least one of an application and a file system, determining whether the write data should be stored in the MLC area or the SLC area based on a data characteristic of the write data or an update characteristic of the write data.

2. The system of claim 1, wherein the data characteristic of the write data or the update characteristic of the write data is received from the at least one of the application and the file system.

3. The system of claim 1, wherein the data characteristic of the write data indicates whether the write data will be frequently accessed by the file system or not.

4. The system of claim 3, wherein the flash transition layer determines that the write data should be written to the SLC area when the write data will be frequently accessed by the file system.

5. The system of claim 3, wherein the flash transition layer determines that the write data should be written to the MLC area when the write data will not be frequently accessed by the file system.

6. The system of claim 3, wherein whether the write data will be frequently accessed or not is determined based on an address of the write data as stored in an external memory, a data header information associated with the write data, an external command or a command type of the external command.

7. The system of claim 1, wherein the update characteristic of the write data indicates whether the address associated with the write data is frequently updated or not.

8. The system of claim 7, wherein the flash transition layer determines that the write data should be written to the SLC area when the address associated with the write data is frequently updated.

9. The system of claim 7, wherein the flash transition layer determines that the write data should be written to the MLC area when the address associated with the write data is not frequently updated.

10. The system of claim 7, wherein the flash transition layer further comprises:

a data block history storage unit determining the update characteristic of the write data based on whether or not a count value indicating a number of times the address associated with the write data has been accessed by the system reaches a threshold value.

11. The system of claim 1, wherein the data characteristic of the write data indicates a data type of the write data.

12. The system of claim 11, wherein the data type of the write data is one of a meta data, a volume information data, an operating system data, an application data or a general data.

13. The system of claim 12, wherein the flash transition layer determines that the write data should be stored in the SLC area when the write data is the meta data or the volume information data.

14. The system of claim 12, wherein the flash transition layer determines that the write data should be stored in the MLC area when the write data is the operating system data, the application data or the general data.

15. The non-volatile memory system comprises:

a non-volatile memory cell array having a plurality of multi-level cells forming a MLC area and a plurality of single-level cells forming a SLC area; and

a flash transition layer receiving a write data from an external source, determining whether the write data should be stored in the MLC area or the SLC area based on a data characteristic signal of the write data or an update characteristic signal of the write data,

wherein the data characteristic signal of the write data or the update characteristic signal of the write data is received from the external source.

16. The system of claim 15, wherein the non-volatile memory system further comprises a flash interface located between the flash transition layer and the non-volatile memory cell array.

17. The system of claim 16, wherein the flash transition layer comprises a mapping unit capable of mapping an address for the write data into a physical address for the non-volatile memory cell array.

18. The system of claim 17, wherein the flash transition layer further comprises a hybrid algorithm unit determining whether the write data should be written to the MLC area or the SLC area based on a data characteristic signal of the write data or an update characteristic signal of the write data.

19. The system of claim 18, wherein the flash transition layer outputs a respective write command identifying the MLC area or the SLC area based on whether the write data should be written to the MLC area or the SLC area.

20. The system of claim 16, wherein the flash transition layer further comprises:

a data block history storage unit including a plurality of entries;

each entry comprising a data block number identifying a corresponding data block, a count value indicating a number of times the corresponding data block has been accessed by the system, and a least recently used value.