Cache-To-Cache Cast-In

• US 20100153647A1
• Filed: 12/16/2008
• Published: 06/17/2010
• Est. Priority Date: 12/16/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Starke, William J., Williams, Derek E., Siegel, Michael S., Guthrie, Guy L., Williams, Phillip G., Ng, Alvan W.
• Granted Patent: US 8,225,045 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0862 with prefetch

Abstract

A data processing system includes a first processing unit and a second processing unit coupled by an interconnect fabric. The first processing unit has a first processor core and associated first upper and first lower level caches, and the second processing unit has a second processor core and associated second upper and lower level caches. In response to a data request, a victim cache line is selected for castout from the first lower level cache. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.

Claims

1. A method of data processing in a data processing system including a plurality of processing units including a first processing unit and a second processing unit coupled by an interconnect fabric, wherein the first processing unit has a first processor core and associated first upper and first lower level caches and the second processing unit has a second processor core and associated second upper and lower level caches, said method comprising:

in response to a data request, selecting a victim cache line to be castout from the first lower level cache;

the first processing unit issuing a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination of the victim cache line; and

in response to a coherence response to the LCO command indicating success of the LCO command, removing the victim cache line from the first lower level cache and holding the victim cache line in the second lower level cache.

2. The method of claim 1, wherein the first and second lower level caches are victim caches.

3. The method of claim 1, wherein the selecting includes:

determining membership of each of a plurality of cache lines within a congruence class in either a first class or a second class; and

selecting as the victim cache line one of one or more cache lines received in the second class.

4. The method of claim 1, and further comprising maintaining in the first class one or more cache lines of the congruence class more likely to be accessed by the first processor core.

5. The method of claim 1, wherein:

the victim cache line is a first victim cache line; and

the method further comprises evicting a second victim cache line from the second lower level cache to make room for the first victim cache line in the second lower level cache.

6. The method of claim 1, wherein said lateral castout command identifies the second lower level cache as the destination.

7. The method of claim 1, and further comprising:

in response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit transmitting the victim cache line to the second lower level cache.

8. A data processing system, comprising:

an interconnect fabric; and

a plurality of processing units coupled to the interconnect fabric, the plurality of processing units including a first processing unit and a second processing unit, wherein the first processing unit has a first processor core and associated first upper and first lower level caches, and wherein the second processing unit has a second processor core and associated second upper and lower level caches;

wherein the first processing unit, in response to a data request, selects a victim cache line to be castout from the first lower level cache and issues a lateral castout (LCO) command on the interconnect fabric, the LCO command identifying the victim cache line to be castout from the first lower level cache and indicating that a lower level cache is an intended destination of the victim cache line; and

wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from the first lower level cache and the second lower level cache holds the victim cache line.

9. The data processing system of claim 8, wherein the first and second lower level caches are victim caches.

10. The data processing system of claim 8, wherein the first processing unit selects the victim cache line by determining membership of each of a plurality of cache lines within a congruence class in either a first class or a second class and selecting as the victim cache line one of one or more cache lines received in the second class.

11. The data processing system of claim 8, wherein the first processing unit maintains in the first class one or more cache lines of the congruence class more likely to be accessed by the first processor core.

12. The data processing system of claim 8, wherein:

the victim cache line is a first victim cache line; and

the second lower level cache evicts a second victim cache line to make room for the first victim cache line in the second lower level cache.

13. The data processing system of claim 8, wherein said lateral castout command identifies the second lower level cache as the destination.

14. The data processing system of claim 8, wherein the first processing unit transmits the victim cache line to the second lower level cache in response to a coherence response to the LCO command indicating success of the LCO command.

15. A processing unit for a data processing system including a plurality of processing units coupled by an interconnect fabric, the processing unit comprising:

the processing unit has a first processor core and associated first upper and first lower level caches;

wherein the processing unit, in response to a data request, selects a victim cache line to be castout from the first lower level cache and issues a lateral castout (LCO) command on the interconnect fabric, the LCO command identifying the victim cache line to be castout from the first lower level cache and indicating that a lower level cache is an intended destination of the victim cache line; and

wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from the first lower level cache for storage in a second lower level cache.

16. The processing unit of claim 15, wherein the first and second lower level caches are victim caches.

17. The processing unit of claim 15, wherein the processing unit selects the victim cache line by determining membership of each of a plurality of cache lines within a congruence class in either a first class or a second class and selecting as the victim cache line one of one or more cache lines received in the second class.

18. The processing unit of claim 15, wherein the processing unit maintains in the first class one or more cache lines of the congruence class more likely to be accessed by the first processor core.

19. The processing unit of claim 15, wherein said lateral castout command identifies the second lower level cache as the destination.

20. The processing unit of claim 15, wherein the first processing unit transmits the victim cache line to the second lower level cache in response to a coherence response to the LCO command indicating success of the LCO command.