ERROR DETECTION IN PHYSICAL INTERFACES FOR POINT-TO-POINT COMMUNICATIONS BETWEEN INTEGRATED CIRCUITS
First Claim
1. An apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“
- ICs”
), the apparatus comprising;
an N bit-to-N+2 (“
N bit/N+2”
) bit physical layer (“
PHY”
) encoder configured to;
insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, andencode said N+1 unencoded data bits to yield N+2 encoded data bits; and
an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit,wherein N represents any integer number of data bits.
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Accused Products
Abstract
An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“ICs”) includes an N bit-to-N+2 (“N bit/N+2”) bit physical layer (“PHY”) encoder configured to insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and encode said N+1 unencoded data bits to yield N+2 encoded data bits. The apparatus further includes an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit, wherein N represents any integer number of data bits.
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Citations
5 Claims
-
1. An apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“
- ICs”
), the apparatus comprising;an N bit-to-N+2 (“
N bit/N+2”
) bit physical layer (“
PHY”
) encoder configured to;insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and encode said N+1 unencoded data bits to yield N+2 encoded data bits; and an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit, wherein N represents any integer number of data bits. - View Dependent Claims (2, 3, 4, 5)
- ICs”
Specification