Prefetch for systems with heterogeneous architectures

• US 20100153934A1
• Filed: 12/12/2008
• Published: 06/17/2010
• Est. Priority Date: 12/12/2008
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lachner, Peter
• Application Number:
  US12/316,585
• Publication Number:
  US 20100153934A1
• Time in Patent Office: Days
• US Class Current: 717/146
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals

Abstract

A compiler for a heterogeneous system that includes both one or more primary processors and one or more parallel co-processors is presented. For at least one embodiment, the primary processors(s) include a CPU and the parallel co-processor(s) include a GPU. Source code for the heterogeneous system may include code to be performed on the CPU but also code segments, referred to as “foreign macro-instructions”, that are to be performed on the GPU. An optimizing compiler for the heterogeneous system comprehends the architecture of both processors, and generates an optimized fat binary that includes machine code instructions for both the primary processor(s) and the co-processor(s). The optimizing compiler compiles the foreign macro-instructions as if they were predefined functions of the CPU, rather than as remote procedure calls. The binary is the result of compiler optimization techniques, and includes prefetch instructions to load code and/or data into the GPU memory concurrently with execution of other instructions on the CPU. Other embodiments are described and claimed.

Claims

1. A method comprising:

generating in an intermediate code representation a prefetch instruction and a launch instruction corresponding to an instruction, in a source program, that indicates an operation to be performed on a second processor; and

performing one or more compiler optimizations on the intermediate code representation to generate a binary file, the binary file including first machine instructions of the target processor for the prefetch instruction and the launch instruction and at least one other instruction, as well including one or more second machine instructions of the second processor to be executed by the second processor responsive to the target processor'"'"'s execution of the launch instruction,

the binary file further being structured so that the at least one other instruction is to be executed on the target processor while the second processor executes the second machine instructions.

2. The method of claim 1, wherein:

said prefetch instruction is a data prefetch instruction.

3. The method of claim 1, wherein:

said prefetch instruction is a code prefetch instruction.

4. The method of claim 1, wherein said binary is structured such that one or more instructions are to be executed on the target processor concurrent with the second processor'"'"'s execution of processing associated with the prefetch instruction.

5. The method of claim 1, wherein:

said binary is structured such that the second machine instructions represent operations to be offloaded to the second processor and executed concurrently with the at least one other instruction to be executed on the first processor.

6. The method of claim 1, wherein:

said binary is structured such that said second machine instructions are interleaved with said first machine instructions.

7. The method of claim 1, wherein said instruction in said source program is a compiler directive.

8. The method of claim 7, wherein said compiler directive is a pragma statement.

9. A system comprising:

a die package that includes a first processor and a second processor, said first and second processors being heterogeneous with respect to each other;

a first memory coupled to said first processor and a second memory coupled to said second processor;

a library to facilitate transport of instructions and data, related to a set of source instructions, between the first processor and the second memory, wherein said second memory is not shared by said first processor;

said first and second processors to execute a single executable code image that has been compiled by an optimizing compiler such that the executable image includes one or more calls to the library to trigger transport of data for the set of source instructions to the second processor while the first processor concurrently executes one or more other instructions.

10. The system of claim 9, wherein:

the second processor is capable of concurrent execution of multiple threads.

11. The system of claim 9, wherein said first memory is a DRAM.

12. The system of claim 9, wherein the first processor is a central processing unit.

13. The system of claim 12, further comprising one or more additional central processing units.

14. The system of claim 9, wherein the second processor is a graphics processing unit.

15. The system of claim 14, wherein the graphics processing unit is to execute multiple threads concurrently.

16. The system of claim 9, wherein the library is stored in the second memory.

17. The system of claim 9, wherein the transported data is source data for the set of source instructions.

18. The system of claim 9, wherein the transported data is machine code instructions of the second processor that are to cause the second processor to perform one or more operations corresponding to the source set of instructions.

19. An article comprising a machine-accessible medium including instructions that when executed cause a system to:

generate in an intermediate code representation a prefetch instruction and a launch instruction corresponding to an instruction, in a source program, that indicates one or more instructions to be performed on a second processor;

wherein said launch instruction is to be executed as a predefined function of a target processor rather than as a remote procedure call; and

perform one or more compiler optimizations on the intermediate code representation to generate a binary file, the binary file including first machine instructions of the target processor for the prefetch instruction and the launch instruction and at least one other instruction, as well including one or more second machine instructions of the second processor to be executed by the second processor responsive to the target processor'"'"'s execution of the launch instruction, the binary file further being structured so that the at least one other instruction is to be executed on the target processor concurrent with the second processor'"'"'s execution of the second machine instructions.

20. The article of claim 19, wherein said prefetch instruction is a data prefetch instruction.

21. The article of claim 19, wherein said prefetch instruction is a code prefetch instruction.

22. The article of claim 19, further comprising instructions that when executed enable the system to construct said binary such that one or more instructions are to be executed on the target processor while the second processor executes processing associated with the prefetch instruction.

23. The article of claim 19, wherein said instruction in said source program is a compiler directive.

24. The article of claim 19, wherein said instruction in said source program is a pragma statement.

25. The article of claim 19, wherein:

said binary is structured such that the second machine instructions represent operations to be offloaded to the second processor and executed concurrently with the at least one other instruction to be executed on the first processor.

26. The article of claim 19, wherein:

said binary is structured such that said second machine instructions are interleaved with said first machine instructions.