STORAGE SYSTEM HAVING PROCESSOR AND INTERFACE ADAPTERS THAT CAN BE INCREASED OR DECREASED BASED ON REQUIRED PERFORMANCE

• US 20100153961A1
• Filed: 03/01/2010
• Published: 06/17/2010
• Est. Priority Date: 02/10/2004
• Status: Abandoned Application

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Watanabe, Naoki, Inoue, Yasuo, Fujimoto, Kazuhisa, Hosoya, Mutsumi, Shimada, Kentaro
• Application Number:
  US12/714,755
• Publication Number:
  US 20100153961A1
• Time in Patent Office: Days
• US Class Current: 718/104
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A storage system is comprised of an interface unit 10 which has an interface with a server 3 or hard drives 2, a memory unit 21 which has a cache memory module 126 for storing data to be read from/written to the server 3 or the hard drives 2 and a control information memory module 127 for storing control information of the system, a processor unit 81 which has a microprocessor for controlling the read/write of data between the server 3 and the hard drives 2, and an interconnection 31, wherein the interface unit 10, memory unit 21 and processor unit 81 are interconnected with the interconnection 31.

Claims

1. A storage system comprising:

a plurality of interface units including a first interface unit and a second interface unit;

a plurality of cache memory units storing data temporarily which is sent from said interface units;

a plurality of processor units controlling data transfer between said interface units and said cache memory units;

a disk device unit including a plurality of disk devices storing data which said processor units control to send from said cache memory units through said second interface unit;

a first backplane connected to said interface units, said cache memory units, and said processor units; and

a second backplane connected to said disk device unit;

wherein said first interface unit connects to a computer through a first cable,

wherein said second interface unit connects to said second backplane through a second cable,

wherein said first backplane including a plurality of connectors, each of said connectors which connects one of said interface units, one of said cache memory units, or one of said processor units,

wherein the number of said interface units is increased or decreased independently of said cache memory units and said processor units by connecting to said first backplane through one of said connectors,

wherein the number of said cache memory units is increased or decreased independently of said interface units and said processor units by connecting to said first backplane through one of said connectors, and

wherein the number of said processor units is increased or decreased independently of said interface units and said cache memory units by connecting to said first backplane through one of said connectors.

2. A storage system according to claim 1,

wherein the number of said interface units is increased or decreased independently of said cache memory units and said processor units based on a required performance,

wherein the number of said cache memory units is increased or decreased independently of said interface units and said processor units based on the required performance,

wherein the number of said processor units is increased or decreased independently of said interface units and said cache memory units based on the required performance.

3. A storage system according to claim 1,

wherein the number of said interface units is increased or decreased independently of said cache memory units and said processor units based on the number of computers which is connected to the first interface unit or the number of disk drive units which is connected to the second interface unit,

wherein the number of said cache memory units is increased or decreased independently of said interface units and said processor units based on the number of computers which is connected to the first interface unit or the number of disk drive unit which is connected to the second interface unit,

wherein the number of said processor units is increased or decreased independently of said interface units and said cache memory units based on the number of computers which is connected to the first interface unit or the number of disk drive units which is connected to the second interface unit.

4. A storage system according to claim 1,

wherein each of said processor units includes a plurality of processors,

wherein each of said processor units allocates each of said processors to processing at said first interface unit or processing at said second interface unit based on a first processing load at said first interface unit and a second processing load at said second interface unit.

5. A storage system according to claim 4,

wherein when said first processing load at said first interface unit is greater than said second processing load at said second interface unit, the number of processors allocated to said first processing load is larger than the number of processors allocated to said second processing load,

wherein when said second processing load at said second interface unit is greater than said first processing load at said first interface unit, the number of processors allocated to said second processing load is larger than the number of processors allocated to said first processing load.

6. A storage system comprising:

a plurality of interface units including a first interface unit and a second interface unit;

a plurality of memory units, each of said memory units including a cache memory module temporarily storing data which is sent from said interface units;

a plurality of processor units controlling data transfer between said interface units and said memory units;

a disk device unit including a plurality of disk devices storing data which said processor units control to send from said memory units through said second interface unit;

wherein each of said interface units is mounted on each of first circuit boards, and each of said memory units is mounted on each of second circuit boards, and each of said processor units is mounted on each of third circuit boards,

wherein said first backplane including a plurality of connectors, and each of said first circuit boards, each of said second circuit boards, or each of said third circuit boards connects to a first backplane through one of said connectors respectively,

wherein the number of first circuit boards is increased or decreased independently of said second circuit boards and said third circuit boards, by connecting to said first backplane through one of said connectors,

wherein the number of second circuit boards is increased or decreased independently of said first circuit boards and said third circuit boards, by connecting to said first backplane through one of said connectors,

wherein the number of third circuit boards is increased or decreased independently of said first circuit boards and said second circuit boards, by connecting to said first backplane through one of said connectors,

wherein said disk device unit connects to a second backplane,

wherein said first interface unit connects to a computer through a first cable,

wherein said second interface unit connects to said second backplane through a second cable,

wherein when each of said processor units receives a write command from said first interface unit, each of said processor units controls to transfer write data from said first interface unit to one of said memory units, and controls to transfer data from said one of said memory units to said second interface unit to store said write data in one of said disk devices.

7. A storage system according to claim 6,

wherein each of said memory units includes a control memory module storing control information which is referred to by said processor units.

8. A storage system according to claim 7,

wherein when each of said processor units receives said write command from said first interface unit, each of said processor units secures memory area in said cache memory module included in one of said memory units to store said write data temporarily by referring to said control information, and notifies said secured memory area to said first interface unit, and instructs said first interface unit to send said write data to said secured memory area in said cache memory module, and instructs said second interface unit to read said write data from said secured memory area and send said write data to said disk drive unit.

9. A storage system according to claim 7,

wherein when each of said processor units receives a read command from said first interface unit, each of said processor units confirms whether a read data is stored in said cache memory module by referring said control information stored in said control memory module,

wherein if said read data is stored in said cache memory module in one of said memory units, each of said processor units notifies a memory area storing said read data in said cache memory module included in one of said memory units, and instructs said first interface unit to read said read data from said memory area and send said read data to said computer.

10. A storage system according to claim 9,

wherein if said read data is not stored in said cache memory module, each of said processor units secures a memory area in said cache memory module included in one of said memory units, and notifies said secured memory area in said cache memory module to said second interface unit, and instructs said second interface unit to send said read data from said disk drive unit,

wherein each of said processor units instructs said first interface unit to read said read data from said secured memory area in said cache memory module and send said read data to said computer.

11. A storage system according to claim 6,

wherein each of said processor units includes a plurality of processors,

wherein each of said processor units allocates each of said processors to processing at said first interface unit or processing at said second interface unit based on a first processing load at said first interface unit and a second processing load at said second interface unit.

12. A storage system according to claim 11,

wherein when said first processing load at said first interface unit is greater than said second processing load at said second interface unit, the number of processors allocated to said first processing load is larger than the number of processors allocated to said second processing load,

wherein when said second processing load at said second interface unit is greater than said first processing load at said first interface unit, the number of processors allocated to said second processing load is larger than the number of processors allocated to said first processing load.

13. A storage system according to claim 6,

wherein a plurality of interface units, a plurality of memory units, and a plurality of memory units are included in a first cluster,

the storage system further comprising:

a plurality of other interface units, a plurality of other memory units, and a plurality of other memory units which are included in a second cluster

wherein said first cluster connects to said second cluster through a switch which is connected to said first backplane.

14. A storage system according to claim 13,

wherein when said write data is stored in another disk drive unit connecting to another second interface unit of said second cluster, each of said processor units controls to transfer said write data from said memory unit to said another second interface unit of said second cluster.