TECHNIQUES FOR DYNAMICALLY ASSIGNING JOBS TO PROCESSORS IN A CLUSTER USING LOCAL JOB TABLES

• US 20100153966A1
• Filed: 12/16/2008
• Published: 06/17/2010
• Est. Priority Date: 12/16/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Basso, Claude, Calvignac, Jean L., Arimilli, Ravi Kumar, Arimilli, Lakshminarayana Baba
• Granted Patent: US 9,396,021 B2
• Time in Patent Office: Days
• US Class Current: 718/105
• CPC Class Codes: G06F 9/4856 resumption being on a different machine, e.g. task migration, virtual machine migration G06F9/5088 takes precedence
• CPC Class Codes: G06F 9/5066 Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs mappping at compile time, see G06F8/451
• CPC Class Codes: G06F 9/5088 involving task migration

Abstract

A technique for operating a high performance computing cluster includes monitoring workloads of multiple processors. The high performance computing cluster includes multiple nodes that each include two or more of the multiple processors. Workload information for the multiple processors is periodically updated in respective local job tables maintained in each of the multiple nodes. Based on the workload information in the respective local job tables, one or more threads are periodically moved to a different one of the multiple processors.

Claims

1. A method of operating a high performance computing cluster, comprising:

monitoring workloads of multiple processors, wherein the high performance computing cluster includes multiple nodes that each include two or more of the multiple processors;

periodically updating workload information for the multiple processors in respective local job tables maintained in each of the multiple nodes; and

periodically moving, based on the workload information in the respective local job tables, one or more threads to a different one of the multiple processors.

2. The method of claim 1, where the workload information is based on utilization of one or more floating-point units included within each of the multiple processors.

3. The method of claim 1, further comprising:

cracking one of the one or more of the threads that is executing on a first processor, included in the multiple processors, based on a first workload of the first processor into at least two secondary threads; and

moving at least one of the at least two secondary threads to a second processor, included in the multiple processors, based on a second workload of the second processor.

4. The method of claim 1, wherein the moving further comprises:

moving identified threads, included in the one or more threads, that communicate above a threshold level to identified processors, included in the multiple processors, that are located physically closer to each other.

5. The method of claim 1, wherein the multiple nodes are arranged in a three-dimensional Taurus topology.

6. The method of claim 1, further comprising:

periodically broadcasting information, related to processor utilization and network utilization at each of the multiple nodes, from each of the multiple nodes to remaining ones of the multiple nodes; and

updating the respective local job tables maintained in each of the multiple nodes based on the broadcast information.

7. The method of claim 1, wherein the multiple processors are included within multiple chip-level multiprocessors.

8. The method of claim 7, wherein at least some of the multiple processors included within different ones of the multiple chip-level multiprocessors are coupled together via host channel adapters and switch fabrics including one or more switches.

9. A high performance computing cluster, comprising:

multiple nodes that each include two or more multiple processors; and

monitoring hardware included in each of the multiple nodes, wherein the monitoring hardware is configured to monitor workloads of the multiple processors, wherein the monitoring hardware is further configured to periodically update workload information for the multiple processors in respective local job tables maintained in each of the multiple nodes, and wherein the high performance computer cluster is configured to periodically move, based on the workload information in the respective local job tables, one or more threads to a different one of the multiple processors.

10. The high performance computing cluster of claim 9, where the workload information is based on utilization of one or more floating-point units included within each of the multiple processors.

11. The high performance computing cluster of claim 9, wherein the high performance computing cluster is further configured to crack one of the one or more of the threads that is executing on a first processor, included in the multiple processors, based on a first workload of the first processor into at least two secondary threads and move at least one of the at least two secondary threads to a second processor, included in the multiple processors, based on a second workload of the second processor.

12. The high performance computing cluster of claim 9, wherein the high performance computing cluster is further configured to move identified threads, included in the one or more threads, that communicate above a threshold level to identified processors, included in the multiple processors, that are located physically closer to each other.

13. The high performance computing cluster of claim 9, wherein the multiple nodes are arranged in a three-dimensional Taurus topology.

14. The high performance computing cluster of claim 9, wherein the high performance computing cluster is further configured to periodically broadcast information, related to processor utilization and network utilization at each of the multiple nodes, from each of the multiple nodes to remaining ones of the multiple nodes and update the respective local job tables maintained in each of the multiple nodes based on the broadcast information.

15. The high performance computing cluster of claim 9, wherein the multiple processors are included within multiple chip-level multiprocessors.

16. The high performance computing cluster of claim 15, wherein at least some of the multiple processors included within different ones of the multiple chip-level multiprocessors are coupled together via host channel adapters and switch fabrics including one or more switches.

17. A method of operating a high performance computing cluster, comprising:

monitoring workloads of multiple processors, wherein the high performance computing cluster includes multiple nodes that each include two or more of the multiple processors;

periodically updating workload information for the multiple processors in respective local job tables maintained in each of the multiple nodes;

periodically moving, based on the workload information in the respective local job tables, one or more threads to a different one of the multiple processors;

cracking one of the one or more of the threads that is executing on a first processor, included in the multiple processors, based on a first workload of the first processor into at least two secondary threads; and

moving at least one of the at least two secondary threads to a second processor, included in the multiple processors, based on a second workload of the second processor.

18. The method of claim 17, where the workload information is based on utilization of one or more floating-point units included within each of the multiple processors.

19. The method of claim 17, wherein the moving further comprises:

moving identified threads, included in the one or more threads, that communicate above a threshold level to identified processors, included in the multiple processors, that are located physically closer to each other.

20. The method of claim 17, wherein the multiple nodes are arranged in a three-dimensional Taurus topology and the multiple processors are included within multiple chip-level multiprocessors, and wherein at least some of the multiple processors included within different ones of the multiple chip-level multiprocessors are coupled together via host channel adapters and switch fabrics including one or more switches.