Quad memory cell and method of making same

• US 20100155689A1
• Filed: 12/19/2008
• Published: 06/24/2010
• Est. Priority Date: 12/19/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Granted Patent: US 7,923,812 B2
• Time in Patent Office: Days
• US Class Current: 257/5
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/22 of the metal-insulator-metal type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels
• CPC Class Codes: H10N 70/8845 Carbon or carbides

Abstract

A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements.

Claims

1. A non-volatile memory device comprising:

a first electrode;

a diode steering element;

at least three resistivity switching storage elements; and

a second electrode;

wherein;

the diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements; and

the second electrode electrically contacts only one of the at least three resistivity switching storage elements.

2. The device of claim 1, wherein the at least three resistivity switching elements comprise four resistivity switching storage elements.

3. The device of claim 1, wherein the diode steering element comprises a tapered diode which contacts the first electrode with a first side and which contacts the at least three resistivity switching storage elements with corners of an opposite second side which is wider than the first side.

4. The device of claim 3, wherein:

the first electrode comprises a first bit line;

the second electrode comprises a first word line; and

each of the at least three resistivity switching storage elements electrically contacts a different word line.

5. The device of claim 4, wherein:

the diode steering element and each of the at least three resistivity switching storage elements comprises a cell of one time programmable memory or a cell of rewritable nonvolatile memory;

the diode steering element comprises a p-n semiconductor diode, a p-i-n semiconductor diode, a metal insulator metal (MIM) diode, or a metal insulator-insulator metal (MIIM) diode; and

the resistivity switching storage elements comprise a resistivity switching material selected from an antifuse dielectric, fuse, diode and antifuse dielectric arranged in a series, a polysilicon memory effect material, a metal oxide or switchable complex metal oxide material, a carbon nanotube material, a graphene switchable resistance material, a phase change material, a conductive bridge element, an electrolyte switching material, a switchable polymer material, or a carbon resistivity switching material.

6. The device of claim 5, wherein a p-type layer of the diode steering element exists only where the resistivity switching storage elements contact the diode steering element.

7. The device of claim 5, wherein a n-type layer of the diode steering element exists only where the resistivity switching storage elements contact the diode steering element.

8. The device of claim 5, wherein the cells comprise a monolithic, three dimensional array of nonvolatile memory cells.

9. The device of claim 1, wherein the at least three resistivity switching elements comprise three resistivity switching storage elements.

10. The device of claim 9, further comprising:

a plurality of diode steering elements,

wherein the plurality of diode steering elements is arranged in unit cells of equilateral triangles.

11. A non-volatile memory device comprising:

a first electrode;

a first diode steering element;

at least three resistivity switching storage elements;

a second diode steering element; and

a second electrode;

wherein;

the first diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements, and

the second diode steering element electrically contacts the second electrode and only one of the at least three resistivity switching storage elements.

12. The device of claim 11, wherein the at least three resistivity switching elements comprise four resistivity switching storage elements.

13. The device of claim 12, wherein:

the first diode steering element, the second diode steering element, and one of the four resistivity switching storage elements comprise a cell of one time programmable memory or a cell of rewritable nonvolatile memory;

the first diode steering element and the second diode steering element comprise a p-n semiconductor diode, a p-i-n semiconductor diode, a metal insulator metal (MIM) diode, or a metal insulator-insulator metal (MIIM) diode; and

the four resistivity switching storage elements comprise a resistivity switching material selected from an antifuse dielectric, fuse, diode and antifuse dielectric arranged in a series, a polysilicon memory effect material, a metal oxide or switchable complex metal oxide material, a carbon nanotube material, a graphene switchable resistance material, a phase change material, a conductive bridge element, an electrolyte switching material, a switchable polymer material, or a carbon resistivity switching material.

14. The device of claim 13, wherein a p-type layer of the diode steering elements exists only where the resistivity switching storage elements contact the diode steering element.

15. The device of claim 13, wherein a n-type layer of the diode steering elements exists only where the resistivity switching storage elements contact the diode steering element.

16. The device of claim 13, wherein the cells comprise a monolithic, three dimensional array of nonvolatile memory cells.

17. The device of claim 16, wherein:

the first diode steering element comprises a tapered diode which electrically contacts the first electrode with a first side and which contacts the at least three resistivity switching storage elements with an opposite second side which is wider than the first side, and

the second diode steering element comprises a tapered diode which electrically contacts the second electrode with a third side and which contacts only one of the at least three resistivity switching storage elements with an opposite fourth side which is wider than the third side.

18. The device of claim 11, wherein the at least three resistivity switching elements comprise three resistivity switching storage elements.

19. The device of claim 18, further comprising:

a plurality of diode steering elements,

wherein the plurality of diode steering elements is arranged in unit cells of equilateral triangles.

20. A non-volatile memory device comprising:

a first diode steering element;

a first bit line electrically contacting the first diode steering element;

at least three resistivity switching storage elements;

a first word line,

wherein the first diode steering element electrically contacts the at least three resistivity switching storage elements, and the first word line electrically contacts only one of the at least three resistivity switching storage elements;

a second diode steering element which is located adjacent to the first diode steering element;

a second bit line electrically contacting the second diode steering element; and

at least three additional resistivity switching storage elements,

wherein the first diode steering element electrically contacts the at least three additional resistivity switching storage elements, and the first word line electrically contacts only one of the at least three additional resistivity switching storage elements; and

a by-pass bit line located between the first and the second bit lines,

wherein the by-pass bit line does not electrically contact the first diode steering element or the second diode steering element.

21. The device of claim 20, wherein the at least three resistivity switching elements comprise four resistivity switching storage elements, and wherein the at least three additional resistivity switching storage elements comprise four additional resistivity switching storage elements.

22. The device of claim 20, wherein the at least three resistivity switching elements comprise three resistivity switching storage elements and wherein the at least three additional resistivity switching storage elements comprise three additional resistivity switching storage elements.

23. The device of claim 20, wherein the first word line directly electrically contacts the one of the least three resistivity switching elements and the first word line directly electrically contacts the one of the least three additional resistivity switching elements such that the direct electrical contact does not pass through a diode.

24. The device of claim 20, further comprising:

a third diode steering element, wherein the third diode steering element is located vertically between the first word line and the at least three resistivity switching storage elements, and wherein the third diode steering element directly electrically contacts the first word line, only one of the at least three resistivity switching storage elements, and only one of the at least three additional resistivity switching storage elements;

a fourth diode steering element which is located adjacent to the third diode steering element;

a second word line, wherein the fourth diode steering element electrically contacts the second word line, only another one of the at least three resistivity switching storage elements, and only another one of the at least three additional resistivity switching storage elements such that the third diode steering element and the fourth diode steering element do not electrically contact common resistivity switching storage elements; and

a by-pass word line located between the first and the second word lines.

25. The device of claim 24, wherein the by-pass word line does not electrically contact the third diode steering element or the fourth diode steering element.

26. A memory array comprising:

a matrix of first diode steering cells arranged in a plurality of rows and a plurality of columns on a first layer of the memory array; and

a plurality of X lines, wherein the X lines are not substantially parallel to the rows;

wherein each of the first diode steering cells contacts at least one of the plurality of X lines, and a number of X lines of the plurality of the X lines is greater than a number of columns of the plurality of columns.

27. The memory array of claim 26 wherein the number of X lines is approximately two times the number of columns.

28. The memory array of claim 26, further comprising:

a plurality of Y lines, wherein the Y lines are not substantially parallel to the columns;

wherein each of the first diode steering cells contacts at least one of the plurality of Y lines, and a number of Y lines of the plurality of the Y lines is greater than a number of rows of the plurality of rows.

29. The memory array of claim 28 wherein the number of Y lines is approximately two times the number of rows.

30. The memory array of claim 29 wherein each of the first diode steering cells comprise:

a first diode; and

a resistivity switching storage element,

wherein the first diode electrically contacts the resistivity switching storage element and one X line, and the resistivity switching storage element also contacts one Y line.

31. The memory array of claim 30 wherein each diode electrically contacts at least three resistivity switching storage elements,

wherein each diode is part of at least three first diode steering cells.

32. The memory array of claim 31 further comprising:

a second diode,

wherein the second diode electrically contacts only one of the at least three resistivity switching storage elements, electrically contacts at least two additional resistivity switching storage elements, and electrically contacts only one Y line.

33. The memory array of claim 32 further comprising:

a matrix of second diode steering cells arranged in a second plurality of rows and a second plurality of columns on a second layer of the memory array; and

a second plurality of Y lines wherein the second Y lines are not substantially parallel to the columns;

wherein each of the second diode steering cells contacts at least one of the second plurality of Y lines, a second number of Y lines of the second plurality of the Y lines is greater than a second number of rows of the second plurality of rows, and the plurality of X lines is shared by the matrix of diode steering cells and matrix of second diode steering cells.