SiC SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS, INTEGRATED CIRCUIT AND MANUFACTURING METHOD

• US 20100155743A1
• Filed: 12/22/2008
• Published: 06/24/2010
• Est. Priority Date: 12/22/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Auerbach, Franz, Rueschenschmidt, Kathrin, Treu, Michael, Haeberlen, Oliver
• Granted Patent: US 8,188,482 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 29/1058 with PN junction gate
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/66909 Vertical transistors, e.g. tecnetrons
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

One aspect includes a semiconductor device with self-aligned contacts, integrated circuit and manufacturing method. One embodiment provides gate control structures. Each of the gate control structures is configured to control the conductivity of a channel region within a silicon carbide substrate by field effect. A contact hole is self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers.

Claims

1. A semiconductor device comprising:

gate control structures each configured to control the conductivity of a channel region within a silicon carbide substrate by field effect; and

a contact being self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers.

2. The semiconductor device of claim 1, wherein a distance between the contact and one of the gate control structures on a level with the channel region is less than 30 nm.

3. The semiconductor device of claim 1, wherein the contact includes a buried portion formed in a cavity within the silicon carbide substrate.

4. The semiconductor device of claim 1, wherein a sidewall profile of the contact is at least partly curved opening up the contact with increasing distance from a surface of the silicon carbide substrate.

5. The semiconductor device of claim 1, wherein a material of an insulating structure that is arranged above the gate control structures and laterally adjoins to at least one of the spacers is different from the material of the spacers.

6. A Junction Field Effect Transistor, comprising:

gate control structures each configured to control the conductivity of a channel region within a silicon carbide substrate by field effect; and

a contact being self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers.

7. The Junction Field Effect Transistor of claim 6, wherein the contact is connected to a bottom gate region of the Junction Field Effect Transistor and the gate control structures include top gate control structures, the channel region being sandwiched between one of the top gate structures and the bottom gate region.

8. The Junction Field Effect Transistor of claim 6, wherein the contact has a same lateral distance to both adjacent gate control structures, respectively.

9. The Junction Field Effect Transistor of claim 7, wherein a source region is embedded in the bottom gate region.

10. The Junction Field Effect Transistor of claim 9, wherein the bottom gate region is self-aligned to the source region.

11. A method for manufacturing a semiconductor device, the method comprising:

forming gate control structures, wherein each of the gate control structures is configured to control the conductivity of a channel region within a silicon carbide substrate by field effect; and

forming a contact being self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers.

12. The method of claim 11, further comprising:

forming semiconductor regions within the silicon carbide substrate by ion implantation of impurities and annealing implant damages prior to formation of the gate control structures.

13. The method of claim 11, further comprising:

extending the contact into the silicon carbide substrate by forming a cavity within the silicon carbide substrate.

14. The method of claim 11, wherein the gate control structures result from patterning a gate control structure layer via a hard mask;

and

the spacers result from forming a spacer layer over the hard mask and removing the spacer layer until the spacers are left.

15. The method of claim 14, comprising forming the spacers by etching the spacer layer resulting in an at least partly curved spacer sidewall profile broadening the spacers with decreasing distance to a surface of the silicon carbide substrate.

16. The method of claim 14, further comprising:

patterning the hard mask so as to leave a remnant portion of the hard mask at least over the gate control structures.

17. The method of claim 16, further comprising leaving an additional remnant portion of the hard mask in a peripheral area of an active cell region.

18. The method of claim 13, comprising carrying out annealing of the implant damages with the blank SiC substrate having no oxide layers formed thereon.

19. A method of manufacturing a Junction Field Effect Transistor within a silicon carbide substrate, the method comprising:

forming gate control structures, wherein each of the gate control structures is configured to control the conductivity of a channel region within a silicon carbide substrate by field effect; and

thereafter

forming a contact being self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers.

20. The method of claim 19, wherein forming the gate control structure includes forming buried gate regions, channel regions and top gate regions, wherein at least one of the buried gate regions, the channel regions and the top gate regions is formed by ion implantation of impurities and subsequent annealing of implant damages.

21. The method of claim 20, further comprising carrying out the annealing of the implant damages with the blank SiC substrate having no oxide layers formed thereon.

22. The method of claim 20, further comprising forming the buried gate regions in self-aligned manner with regard to previously formed source regions.

23. The method of claim 19, wherein the gate control structures result from patterning a gate control structure layer via a hard mask;

and

the spacers result from forming a spacer layer over the hard mask and removing the spacer layer until the spacers are left.

24. The method of claim 23, further comprising forming the spacers by etching the spacer layer resulting in an at least partly curved spacer sidewall profile broadening the spacers with decreasing distance to a surface of the silicon carbide substrate.

25. The method of claim 19, further comprising:

patterning the hard mask so as to leave a remnant portion of the hard mask at least over the gate control structures.