TRENCH TYPE MOSFET DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20100155838A1
• Filed: 12/21/2009
• Published: 06/24/2010
• Est. Priority Date: 12/23/2008
• Status: Abandoned Application

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Jung, Ji-Houn
• Application Number:
  US12/643,413
• Publication Number:
  US 20100155838A1
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench type Metal Oxide Silicon Field Effect Transistor (MOSFET) device and a method of manufacturing a trench type MOSFET device. A trench type MOSFET device may include a wide-trench source contact poly which may be formed on and/or over a space between deep-trench gate polys on and/or over a trench type power MOSFET device. An electric field may be formed around a source contact poly and/or a gate poly. A relatively strong electric field may be minimized at an edge between a trench gate and a source. Leakage may be minimized and/or reliability may be maximized.

Claims

1. An apparatus comprising:

at least two trench gates;

a trench source contact between said at least two trench gates comprising a smaller depth relative to said at least two trench gates; and

an ion-injected active region layer between said source contact and said at least two gates.

2. The apparatus of claim 1, wherein at least one of said at least two trench gates and said source contact comprise polysilicon films.

3. The apparatus of claim 1, wherein said at least two trench gates comprise a gate oxide film having a thickness between approximately 200 Å

and 300 Å

.

4. The apparatus of claim 1, wherein said source contact comprises a polysilicon film having a thickness between approximately 4500 Å

and 10000 Å

.

5. The apparatus of claim 1, wherein said at least two trench gates, said trench source contact and said ion-injected active region layer are formed over a semiconductor substrate.

6. The apparatus of claim 1, wherein said an ion-injected active region layer comprises N+ ions.

7. The apparatus of claim 1, comprising a Metal Oxide Silicon Field Effect Transistor device.

8. The apparatus of claim 7, wherein current flow between a source and a drain that leans to at least one of said at least two trench gates is minimized when power is applied to said at least two trench gates.

9. A method comprising:

forming a trench region to form at least two trench gates and a trench source contact;

etching back a polysilicon film formed over said trench region to form said at least two gates and said source contact;

forming a photoresist mask to expose a region substantially excluding said at least two trench gates and said trench source contact; and

forming an active region layer between said source contact and said at least two gates by ion injection using said photoresist mask.

10. The method of claim 9, wherein said etching back simultaneously forms said at least two gates and said source contact.

11. The method of claim 9, wherein said source contact is formed between said at least two trench gates.

12. The method of claim 11, wherein said source contact comprises a smaller depth relative to said at lest two trench gates.

13. The method of claim 11, wherein said source contact comprises a polysilicon film.

14. The method of claim 13, where said polysilicon film comprises a thickness between approximately 4500 Å

and 10000 Å

.

15. The method of claim 9, wherein forming said photoresist mask comprises:

applying a photoresist film over an entire surface of a semiconductor substrate including said at least two trench gates and said source contact; and

patterning said photoresist film such that said at least two trench gates and said source contact are not substantially exposed.

16. The method of claim 9, wherein said at least two trench gates and said source contact comprise polysilicon films

17. The method of claim 9, wherein said at least two trench gates comprise a gate oxide film having a thickness between approximately 200 Å

and 300 Å

.

18. The method of claim 9, wherein said ion injection comprises using N+ ions.

19. The method of claim 9, comprising forming a Metal Oxide Silicon Field Effect Transistor device.

20. The method of claim 19, wherein current flow between a source and a drain that leans to at least one of said at least two trench gates is minimized when power is applied to said at least two trench gates.