BODY CONTACTED HYBRID SURFACE SEMICONDUCTOR-ON-INSULATOR DEVICES

• US 20100155842A1
• Filed: 12/23/2008
• Published: 06/24/2010
• Est. Priority Date: 12/23/2008
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Anderson, Brent A.
• Granted Patent: US 8,227,867 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region.

Claims

1. A semiconductor structure comprising:

a semiconductor fin having a first sidewall, a second sidewall, and a substantially horizontal top surface and located directly on an insulator layer located on a substrate, wherein said first and second sidewalls are substantially parallel to each other and substantially vertical;

a body region located within said semiconductor fin and having a doping of a first conductivity type and vertically abutting said insulator layer;

a first source region located within a first end of said semiconductor fin and directly on said first sidewall and having a doping of a second conductivity type, wherein said second conductivity type is the opposite of said first conductivity type;

a second source region located within said first end of said semiconductor fin and directly on said second sidewall and having a doping of said second conductivity type; and

a metal semiconductor alloy portion abutting said first source region, said second source region, and a top surface of a portion of said semiconductor fin having a doping of said first conductivity type and located between said first source region and said second source region.

2. The semiconductor structure of claim 1, further comprising a drain region located within a second end of said semiconductor fin and having a doping of said second conductivity type, wherein said drain region is separated from said first and second source regions by said body region, and wherein said second end is located at an opposite side of said first end of said semiconductor fin.

3. The semiconductor structure of claim 2, wherein said drain region is located directly on said first sidewall and directly on said second sidewall.

4. The semiconductor structure of claim 3, wherein said drain region is contiguous and includes a portion located directly on an end wall of said semiconductor fin, wherein said end wall is substantially perpendicular to said first sidewall and said second sidewall and is directly adjoined to said first sidewall and said second sidewall.

5. The semiconductor structure of claim 3, further comprising:

a first gate dielectric abutting a middle portion of said first sidewall;

a second gate dielectric abutting a middle portion of said second sidewall; and

a gate conductor abutting said first gate dielectric and said second gate dielectric.

6. The semiconductor structure of claim 5, wherein said first gate dielectric does not abut said second gate dielectric.

7. The semiconductor structure of claim 3, wherein an edge of said first source region and an edge of said second source region is substantially aligned to an edge of said gate conductor, and wherein an edge of said drain region is substantially aligned to another edge of said gate conductor.

8. The semiconductor structure of claim 3, further comprising a dielectric fin cap portion vertically abutting said body region and said drain region.

9. The semiconductor structure of claim 8, wherein said dielectric fin cap portion overlies an entirety of said drain region, and wherein an edge of said dielectric fin cap portion is substantially aligned to said gate conductor.

10. The semiconductor structure of claim 3, further comprising:

a dielectric fin cap portion vertically abutting said body region; and

a gate conductor vertically abutting said dielectric fin cap portion, wherein sidewalls of said gate conductor are substantially vertically coincident with sidewalls of said dielectric fin cap portion.

11. The semiconductor structure of claim 10, wherein said drain region is contiguous and includes a portion located directly on a top surface of said semiconductor fin and extending from an end wall of said semiconductor fin to an edge of said dielectric fin cap portion.

12. The semiconductor structure of claim 11, wherein a portion of said body region underlies a portion of said drain region.

13. The semiconductor structure of claim 11, wherein a boundary between said body region and said drain region extends from a top surface of said semiconductor portion to said insulator layer, wherein an entirety of said boundary is substantially vertically coincident with an edge of said gate conductor.

14. The semiconductor structure of claim 1, wherein said portion of said semiconductor fin having a doping of said first conductivity type is a portion of said body region.

15. The semiconductor structure of claim 1, wherein said portion of said semiconductor fin is a first-conductivity-type doped region having a dopant concentration greater than a dopant concentration of said body region.

16. The semiconductor structure of claim 15, wherein a dopant concentration of said first source region and said second source region is greater than said dopant concentration of said first-conductivity-type doped region.

17. The semiconductor structure of claim 1, wherein an entirety of said semiconductor fin is single crystalline.

18. A method of forming a semiconductor structure comprising:

forming a semiconductor fin having a first sidewall, a second sidewall, and a substantially horizontal top surface and located directly on an insulator layer and having a doping of a first conductivity type, wherein said first and second sidewalls are substantially parallel to each other and substantially vertical;

forming a first source region having a doping of a second conductivity type directly on said first sidewall within a first end of said semiconductor fin, wherein said second conductivity type is the opposite of said first conductivity type;

forming a second source region having a doping of said second conductivity type directly on said second sidewall within said first end of said semiconductor fin; and

forming a metal semiconductor alloy portion directly on said first source region, said second source region, and a top surface of a portion of said semiconductor fin having a doping of said first conductivity type and located between said first source region and said second source region.

19. The method of claim 18, further comprising forming a drain region within a second end of said semiconductor fin and having a doping of said second conductivity type, wherein said drain region does not abut said first and second source regions, and wherein said second end is located at an opposite side of said first end.

20. The method of claim 19, further comprising:

providing a semiconductor-on-insulator (SOI) layer including said insulator layer and a top semiconductor layer;

forming a dielectric fin cap layer on said top semiconductor layer; and

patterning said dielectric fin cap layer and said top semiconductor layer, wherein a remaining portion of said dielectric fin cap layer constitutes a dielectric fin cap portion, wherein a remaining portion of said top semiconductor layer constitutes said semiconductor fin, and wherein said first sidewall and said second sidewall are substantially vertically coincident with sidewalls of said dielectric fin cap portion.

21. The method of claim 20, wherein said first source region, said second source region, and said drain region are formed by implantation of ions of said second conductivity type.

22. The method of claim 20, wherein said drain region is contiguous and includes a portion located directly on an end wall of said semiconductor fin, wherein said end wall is substantially perpendicular to said first sidewall and said second sidewall and is directly adjoined to said first sidewall and said second sidewall.

23. The method of claim 20, further comprising:

forming a first gate dielectric directly on a middle portion of said first sidewall;

forming a second gate dielectric directly on a middle portion of said second sidewall; and

forming a gate conductor directly on said first gate dielectric, said second gate dielectric, and said dielectric fin cap portion.

24. The method of claim 20, wherein said dielectric fin cap portion overlies an entirety of said drain region, and wherein an edge of said dielectric fin cap portion is substantially aligned to said gate conductor.

25. The method of claim 20, further comprising implanting dopants of said first conductivity type through a portion of said substantially horizontal top surface of said semiconductor fin located between said first source region and said second source region to form a first-conductivity-type doped region.

26. A method of forming a semiconductor structure comprising:

forming a semiconductor fin having a first sidewall, a second sidewall, and a substantially horizontal top surface and located directly on an insulator layer and having a doping of a first conductivity type, wherein said first and second sidewalls are substantially parallel to each other and substantially vertical;

forming a recombination-center-containing semiconductor region directly underneath said substantially horizontal top surface and including an amorphized semiconductor material and having a doping of said first conductivity type; and

forming a metal semiconductor alloy portion directly on said recombination-center-containing semiconductor region and at least one source region formed within said semiconductor fin and having a doping of a second conductivity type, wherein said second conductivity type is the opposite of said first conductivity type.