SILICON INTERPOSER TESTING FOR THREE DIMENSIONAL CHIP STACK

• US 20100155888A1
• Filed: 12/24/2008
• Published: 06/24/2010
• Est. Priority Date: 12/24/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Maldonado, Julio Alejandro, Weekly, Roger Donell, Zhou, Tingdong, Christo, Michael Anthony
• Granted Patent: US 7,863,106 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/30105 Capacitance

Abstract

A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer. The method thus provides same-sided probe testing of the interposer. The method also provides for loading or power application to the conductive glass handler and testing of circuits and interconnects on the test side of the silicon interposer.

Claims

1. A method of manufacturing a semiconductor interposer, comprising:

forming an interposer subassembly of semiconductor material including first, second and third interconnects extending from a first surface of the interposer subassembly to a second surface of the interposer subassembly, the first and second surfaces being opposed major surfaces;

forming a non-conductive layer on the first surface of the interposer subassembly;

selectively removing portions of the non-conductive layer at the first and second interconnects to form open regions at the first and second interconnects, thus forming remaining non-conductive layer portions other than at the first and second interconnects; and

applying a conductive adhesive layer adjacent the first surface of the interposer subassembly covering the open regions and remaining non-conductive layer portions.

2. The method of claim 1, further comprising positioning a conductive glass handler on the conductive adhesive layer adjacent the first surface of the interposer subassembly, thus forming the semiconductor interposer.

3. The method of claim 1, further comprising positioning a first test probe on the first interconnect at the second surface of the interposer subassembly and positioning a second test probe on the second interconnect at the second surface of the interposer subassembly.

4. The method of claim 3, further comprising supplying a test voltage across the first and second probes at the second surface of the semiconductor interposer such that current flows from the first probe, through the first interconnect, through the adhesive layer, through the second interconnect to the second probe, the second surface of the semiconductor interposer thus forming a test side that provides same-sided testing of the semiconductor interposer via the first and second probes.

5. The method of claim 1, further comprising:

positioning a first test probe on the first interconnect at the second surface of the interposer subassembly; and

supplying a test voltage on the conductive glass handler of the semiconductor interposer.

6. The method of claim 1, further comprising:

positioning a first test probe on the first interconnect at the second surface of the interposer subassembly; and

supplying a test voltage between the conductive glass handler and the first test probe test interconnects in the semiconductor interposer.

7. The method of claim 1, further comprising forming an electronic circuit between the first and second interconnects within the semiconductor interposer subassembly.

8. The method of claim 7, wherein the electronic circuit is a deep trench capacitor.

9. The method of claim 1, further comprising forming respective filled-through vias at the first, second and third interconnects adjacent the second surface of the interposer subassembly.

10. The method of claim 1, further comprising forming respective bonding pads at the first, second and third interconnects adjacent the first surface of the interposer subassembly.

11. The method of claim 4, further comprising attaching a flip chip carrier at the second surface of the interposer subassembly.

12. The method of claim 11, further comprising removing the conductive glass handler from the interposer subassembly.

13. The method of claim 12, further comprising attaching an integrated circuit die to the silicon interposer.

14. A semiconductor interposer, comprising:

an interposer subassembly of semiconductor material including first, second and third interconnects extending from a first surface of the interposer subassembly to a second surface of the interposer subassembly, the first and second surfaces being opposed major surfaces;

a non-conductive layer on the first surface of the interposer, the non-conductive layer including open regions at the first and second interconnects where the non-conductive layer is removed, thus forming remaining non-conductive layer portions other than at the first and second interconnects; and

a conductive adhesive layer adjacent the first surface of the interposer subassembly covering the open regions and remaining non-conductive layer portions.

15. The semiconductor interposer of claim 14, further comprising a conductive glass handler situated on the conductive adhesive layer adjacent the first surface of the interposer subassembly.

16. The semiconductor interposer of claim 14, wherein the first interconnect is adapted to be coupled to a first test probe at the second surface of the interposer assembly and the second interconnect is adapted to be coupled to a second test probe at the second surface of the interposer subassembly.

17. The semiconductor interposer of claim 14, further comprising an electronic circuit coupled between the first and second interconnects within the semiconductor interposer subassembly.

18. The semiconductor interposer of claim 17, wherein the electronic circuit is a deep trench capacitor.

19. The semiconductor interposer of claim 14, wherein the first, second and third interconnects include respective filled-through vias adjacent the second surface of the interposer subassembly.

20. The semiconductor interposer of claim 14, wherein the first, second and third interconnects include respective bonding pads adjacent the first surface of the interposer subassembly.

21. The semiconductor interposer of claim 15, wherein a flip chip carrier is attached to the second surface of the interposer subassembly.

22. The semiconductor interposer of claim 21, wherein an integrated circuit die is attached adjacent the first surface of the interposer subassembly after removal of the glass handler from the interposer subassembly.