Method for Forming Thin Film Resistor and Terminal Bond Pad Simultaneously

• US 20100155893A1
• Filed: 12/23/2008
• Published: 06/24/2010
• Est. Priority Date: 12/23/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: CHEN, Fen, HE, Zhong-Xiang, MALINOWSKI, John C., STAMPER, Anthony K., GAMBINO, Jeffrey P., LEE, Tom C.
• Granted Patent: US 8,563,336 B2
• Time in Patent Office: Days
• US Class Current: 257/537
• CPC Class Codes: H01C 17/075 by thin film techniques H01C17/20 takes precedence
• CPC Class Codes: H01C 7/006 Thin film resistors
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/24 with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01016 : Sulfur [S]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.

Claims

1. A method of forming a semiconductor structure, comprising:

simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.

2. The method of claim 1, wherein the simultaneously forming comprises:

depositing a layer of resistor material over substantially all exposed upper surfaces of the semiconductor structure, including exposed portions of the terminal wire and the two wires; and

selectively removing portions of the layer of resistor material to form the terminal bond pad and the thin film resistor.

3. The method of claim 2, wherein the layer of resistor material comprises a refractory metal and has a thickness in a range of about 30 to about 100 nm.

4. The method of claim 3, wherein the refractory metal comprises tantalum nitride (TaN).

5. The method of claim 1, wherein the terminal wire and the two wires are arranged in an uppermost wiring level of the semiconductor structure.

6. The method of claim 1, wherein:

the two other wires are associated with a high speed device, and

the thin film resistor conductively links the two other wires.

7. The method of claim 1, further comprising forming a cap over a high current wire simultaneously with the terminal bond pad and the thin film resistor, wherein the cap reduces electromigration effects in the high current wire.

8. The method of claim 1, further comprising forming a pad film on the terminal bond pad.

9. The method of claim 8, wherein the pad film is configured to be connected to a wire bond or controlled collapse chip connection (C4) solder ball attachment.

10. The method of claim 8, wherein the semiconductor structure is devoid of a terminal metal (TD) aluminum pad structure.

11. The method of claim 8, wherein the forming the pad film comprises:

depositing a pad film layer over substantially all exposed upper surfaces of the semiconductor structure;

photolithographic masking the pad film layer; and

etching away portions of the pad film layer to form the pad film.

12. The method of claim 8, wherein the forming the pad film comprises:

forming photoresist over selected exposed upper surfaces of the semiconductor structure, leaving at least a portion of the terminal bond pad exposed;

depositing a pad film layer over the photoresist and the exposed portion of the terminal bond pad; and

lifting off the photoresist.

13. The method of claim 8, wherein the forming the pad film comprises fabricating the pad film on the terminal bond pad using damascene processes.

14. The method of claim 1, further comprising:

forming a passivation layer over the terminal bond pad and the thin film resistor, and

forming an opening in the passivation layer over the terminal bond pad.

15. A method of forming a semiconductor structure, comprising:

forming a diffusion barrier capping layer on an uppermost wiring level in which a plurality of wires are formed;

forming an isolation layer on the diffusion barrier capping layer;

forming openings in the diffusion barrier capping layer and the isolation layer over the plurality of wires;

forming a layer of refractory metal over exposed upper surfaces of the isolation layer and the plurality of wires; and

removing portions of the layer of refractory metal while leaving other portions of the layer of refractory metal on the plurality of wires.

16. The method of claim 15, wherein:

the plurality of wires comprises a terminal wire, two related wires, and another wire, and

the removing portions of the layer of refractory metal while leaving other portions of the layer of refractory metal on the plurality of wires simultaneously forms;

a terminal bond pad on the terminal wire, a thin film resistor between the two related wires, and a cap on the other wire.

17. The method of claim 16, wherein:

the forming openings in the diffusion barrier capping layer and the isolation layer comprises removing portions of the diffusion barrier capping layer and the isolation layer between the two related wires; and

the forming the layer of refractory metal comprises depositing the refractory metal on the uppermost wiring level between the two related wires.

18. The method of claim 16, further comprising forming a terminal pad film on the terminal bond pad.

19. A semiconductor structure, comprising:

a last wiring level including a terminal wire, two related wires, and another wire formed in a dielectric material layer;

at least one of a diffusion barrier layer and an isolation layer formed on the dielectric material layer;

a terminal bond pad formed on the terminal wire;

a thin film resistor formed on and conductively linking the two related wires;

a cap formed on the other wire;

a passivation layer formed over the terminal bond pad, the thin film resistor, and the cap; and

an opening formed in the passivation layer over the terminal bond pad,

wherein the terminal bond pad, the thin film resistor, and the cap are composed of portions of a common layer of refractory metal.

20. A method of forming a semiconductor device, comprising:

simultaneously forming a thin film resistor and a refractory metal cap over a lower wire, wherein the lower wire is in an intermediate wiring level (n);

forming a next wiring level (n+1) over the thin film resistor and the cap;

forming an upper wire in the next wiring level (n+1) conductively connected to the cap; and

forming two related wires in the next wiring level (n+1) conductively connected to the thin film resistor.

21. The method of claim 20, wherein the simultaneously forming comprises:

patterning a barrier layer to expose a portion of the lower wire, wherein the barrier layer includes at least one of a diffusion barrier layer and an isolation oxide layer;

forming a layer of refractory metal on the portion of the lower wire and the barrier layer; and

selectively removing portions of the layer of refractory metal to form the thin film resistor and the cap.

22. The method of claim 20, wherein the thin film resistor and the refractory metal cap comprise portions of a common layer of refractory metal.

23. The method of claim 22, wherein the refractory metal comprises tantalum nitride (TaN).

24. The method of claim 20, further comprising:

forming a first via between the upper wire and the cap;

forming a second via between a first one of the two related wires and the thin film resistor; and

forming a third via between a second one of the two related wires and the thin film resistor.

25. A semiconductor structure, comprising:

an intermediate wiring level comprising a first wire;

a barrier layer including at least one of a diffusion barrier layer and an isolation oxide layer formed over the intermediate wiring level;

a cap formed on an upper surface of the first wire;

a thin film resistor formed on the barrier layer;

a next wiring level formed over the cap and the thin film resistor;

a second wire formed in the next wiring level and in electrical contact with the cap;

third and fourth wires formed in the next wiring level and in electrical contact with the thin film resistor,

wherein the cap and the thin film resistor are composed of portions of a common layer of refractory metal.