LOW-DROPOUT VOLTAGE REGULATOR AND OPERATING METHOD OF THE SAME

• US 20100156364A1
• Filed: 12/10/2009
• Published: 06/24/2010
• Est. Priority Date: 12/24/2008
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Advanced Technologies Inc. (f/k/a Tessera Advanced Technologies, Inc.) (Adeia Inc.)
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Cho, Sung-Il, Pang (Ha), Sung-Man (Chang woo)
• Granted Patent: US 8,040,118 B2
• Time in Patent Office: Days
• US Class Current: 323/280
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: G05F 1/573 with overcurrent detector

Abstract

A low-dropout (LDO) voltage regulator that includes an error amplifier which compares a reference voltage with a feedback voltage of an output voltage and outputs an error signal based on the result of the comparison, the error amplifier being biased by an input voltage; a first MOS transistor having a gate electrically connected to the error signal, a source electrically connected to the input voltage and a drain electrically connected to the output voltage; a voltage divider which transmits a predetermined part of the output voltage to the error amplifier as feedback voltage; and a level limiter which limits a level of the output voltage from changing beyond and below an offset voltage when a level of a load current changes. In accordance with embodiments, A predetermined number of comparators and MOS transistor type-switches are provided to enhance the slew ratio of the regulated output voltage and to reduce standby electricity consumption.

Claims

1. A low-dropout (LDO) voltage regulator comprising:

an error amplifier which compares a reference voltage with a feedback voltage of an output voltage and outputs an error signal based on the result of the comparison, the error amplifier being biased by an input voltage;

a first MOS transistor having a gate electrically connected to the error signal, a source electrically connected to the input voltage and a drain electrically connected to the output voltage;

a voltage divider which transmits a predetermined part of the output voltage to the error amplifier as feedback voltage; and

a level limiter which limits a level of the output voltage from changing beyond and below an offset voltage when a level of a load current changes.

2. The LDO voltage regulator of claim 1, wherein the level limiter comprises:

a decrease limiter which limits the output voltage from decreasing below a low point of the offset voltage when the load current increases; and

an increase limiter which limits the output voltage from increasing beyond a high point of the offset voltage when the load current decreases.

3. The LDO voltage regulator of claim 2, wherein the error amplifier comprises:

a second MOS transistor comprising a source electrically connected to the input voltage and a gate electrically connected to a positive bias voltage;

a third MOS transistor comprising a source electrically connected to the input voltage and a gate and a drain electrically connected to each other;

a fourth MOS transistor comprising a source electrically connected to the input voltage, a gate electrically connected to the gate of the third MOS transistor and a drain electrically connected to the gate of the first MOS transistor;

a fifth MOS transistor comprising a source electrically connected to the gate/drain of the third MOS transistor and a drain electrically connected to the ground;

a sixth MOS transistor comprising a source electrically connected to both the gate of the fourth MOS transistor and the gate of the first MOS transistor and a drain electrically connected to the ground;

a seventh MOS transistor comprising a source electrically connected to the drain of the second MOS transistor and a gate electrically connected to the reference voltage;

an eighth MOS transistor comprising a source electrically connected to the drain of the second MOS transistor and a gate electrically connected to the feedback voltage;

a ninth MOS transistor comprising a source and a gate electrically connected to both the drain of the seventh MOS transistor and the gate of the fifth MOS transistor and a drain electrically connected to the ground; and

a tenth MOS transistor comprising a source and a gate electrically connected to both the drain of the eighth MOS transistor and the gate of the sixth MOS transistor and a drain electrically connected to the ground.

4. The LDO voltage regulator of claim 2, wherein the increase limiter comprises:

a second switch which switches between the input voltage and the gate of the first MOS transistor in response to a second switching signal;

a second synthesizer which synthesizes the reference voltage and the high point of the offset voltage; and

a second comparator which compares an output of the second synthesizer with the feedback voltage and outputs the second switching signal based on the result of the comparison.

5. The LDO voltage regulator of claim 2, wherein the decrease limiter comprises:

a first switch which switches between the gate of the first MOS transistor and a ground in response to a first switching signal;

a first synthesizer which synthesizes the reference voltage and the low point of the offset voltage; and

a first comparator which compares an output of the first synthesizer and the feedback voltage and outputs the first switching signal based on the result of the comparison.

6. The LDO voltage regulator of claim 5, wherein the decrease limiter further comprises:

a third switch which switches between the first switch and the ground when the error amplifier operates.

7. The LDO voltage regulator of claim 6, wherein the increase limiter further comprises:

a fourth switch which switches between the input voltage and the second switch when the error amplifier operates.

8. The LDO voltage regulator of claim 7, wherein the error amplifier comprises:

a second MOS transistor comprising a source electrically connected to the input voltage and a gate electrically connected to a positive bias voltage;

a third MOS transistor comprising a source electrically connected to the input voltage and a gate and a drain electrically connected to each other;

a fourth MOS transistor comprising a source electrically connected to the input voltage, a gate electrically connected to the gate of the third MOS transistor and a drain electrically connected to the gate of the first MOS transistor;

a fifth MOS transistor comprising a source electrically connected to the gate/drain of the third MOS transistor and a drain electrically connected to the ground;

a sixth MOS transistor comprising a source electrically connected to both the gate of the fourth MOS transistor and the gate of the first MOS transistor and a drain electrically connected to the ground;

a seventh MOS transistor comprising a source electrically connected to the drain of the second MOS transistor and a gate electrically connected to the reference voltage;

an eighth MOS transistor comprising a source electrically connected to the drain of the second MOS transistor and a gate electrically connected to the feedback voltage;

a ninth MOS transistor comprising a source and a gate electrically connected to both the drain of the seventh MOS transistor and the gate of the fifth MOS transistor and a drain electrically connected to the ground; and

a tenth MOS transistor comprising a source and a gate electrically connected to both the drain of the eighth MOS transistor and the gate of the sixth MOS transistor and a drain electrically connected to the ground.

9. The LDO voltage regulator of claim 8, wherein the gate of the sixth transistor comprises a signal which controls the switching of the first switch.

10. The LDO voltage regulator of claim 8, wherein the gate of the fourth transistor comprises a signal which controls the switching of the fourth switch.

11. The LDO voltage regulator of claim 8, wherein the first switch comprises an eleventh MOS transistor having a gate electrically connected to the first switching signal and a source/drain electrically connected to both the gate of the first MOS transistor and the ground.

12. The LDO voltage regulator of claim 11, wherein the third switch comprises a thirteenth MOS transistor having a gate electrically connected to the gate of the sixth MOS transistor and the gate of the tenth MOS transistor and a source/drain electrically connected to both the drain of the eleventh MOS transistor and the ground.

13. The LDO voltage regulator of claim 8, wherein the second switch comprises a twelfth MOS transistor having a source electrically connected to the input voltage, a gate electrically connected to the second switching signal and a drain electrically connected to the gate of the first MOS transistor.

14. The LDO voltage regulator of claim 13, wherein the fourth switch comprises a fourteenth MOS transistor having a gate electrically connected to the gate of the third MOS transistor and the gate of the fourth MOS transistor, a source electrically connected to the input voltage and a drain electrically connected to the source of the twelfth MOS transistor.

15. The LDO voltage regulator of claim 1, wherein the voltage divider comprises a first resistance and a second resistance electrically connected in series between the output voltage and the ground.

16. The LDO voltage regulator of claim 15, wherein the feedback voltage is electrically connected between the first resistance and the second resistance.

17. A low-dropout (LDO) voltage regulator comprising:

an error amplifier comprising a plurality of transistors which compares a reference voltage with a feedback voltage of an output voltage and outputs an error signal based on the result of the comparison, the error amplifier being biased by an input voltage;

a first MOS transistor having a gate electrically connected to the error signal, a source electrically connected to the input voltage and a drain electrically connected to the output voltage;

a voltage divider which transmits a predetermined part of the output voltage to the error amplifier as feedback voltage, the voltage divider including a first resistance and a second resistance electrically connected in series between the output voltage and the ground; and

a level limiter which limits a level of the output voltage from changing beyond and below an offset voltage when a level of a load current changes.

18. The LDO voltage regulator of claim 17, wherein the plurality of transistors comprises:

a second transistor comprising a source electrically connected to the input voltage and a gate electrically connected to a positive bias voltage;

a third transistor comprising a source electrically connected to the input voltage and a gate and a drain electrically connected to each other;

a fourth transistor comprising a source electrically connected to the input voltage, a gate electrically connected to the gate of the third transistor and a drain electrically connected to the gate of the first transistor;

a fifth transistor comprising a source electrically connected to the gate/drain of the third MOS transistor and a drain electrically connected to the ground;

a sixth transistor comprising a source electrically connected to both the gate of the fourth transistor and the gate of the first transistor and a drain electrically connected to the ground;

a seventh transistor comprising a source electrically connected to the drain of the second transistor and a gate electrically connected to the reference voltage;

an eighth transistor comprising a source electrically connected to the drain of the second transistor and a gate electrically connected to the feedback voltage;

a ninth transistor comprising a source and a gate electrically connected to both the drain of the seventh transistor and the gate of the fifth transistor and a drain electrically connected to the ground; and

a tenth transistor comprising a source and a gate electrically connected to both the drain of the eighth transistor and the gate of the sixth transistor and a drain electrically connected to the ground.

19. A method of operating a LDO voltage regulator comprising:

synthesizing a reference voltage and an offset voltage; and

then

limiting a level of an output voltage from changing beyond and below the offset voltage when a level of a load current changes by comparing a feed-backed part of an output voltage and the result of the synthesizing.

20. The method of claim 19, wherein limiting the level of the output voltage comprises:

limiting the output voltage from decreasing below a low point of the offset voltage when the load current increases; and

then

limiting the output voltage from increasing beyond a high point of the offset voltage when the load current decreases.