Hot-Electron Injection Testing of Transistors on a Wafer

• US 20100156454A1
• Filed: 12/24/2008
• Published: 06/24/2010
• Est. Priority Date: 12/24/2008
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Weir, Bonnie Elaine
• Granted Patent: US 7,898,277 B2
• Time in Patent Office: Days
• US Class Current: 324/762.80
• CPC Class Codes: G01R 31/2648 Characterising semiconductor materials testing of materials or semi-finished products G01R31/2831; testing during manufacture H01L22/00

Abstract

A hot-carrier injection (HCI) test that permits rapid screening of integrated circuit wafers susceptible to possible HCI-induced failures is disclosed. A method is described that determines transistor stress voltages that results in a transistor HCI-induced post-stress drain current differing from a pre-stress drain current within a desired range. These stress voltages are determined using a wafer with acceptable HCI susceptibility. Additional wafers to be tested are first tested using a described method that uses the determined transistor stress voltages to quickly screen the wafers for HCI susceptibility and, if HCI susceptibility is found, then additional conventional HCI testing may be applied to the susceptible wafers.

Claims

1. A method of hot-carrier injection screening of a wafer, the method comprising:

a) providing a wafer having at least one MOSFET thereon, the MOSFET having at least a gate, a drain, and a threshold voltage;

b) applying a gate test voltage to the gate and a drain test voltage to the drain of the MOSFET and measuring an initial current flow in the drain;

c) applying, during a stress time period, a gate stress voltage to the gate and a drain stress voltage to the drain of the MOSFET; and

d) applying, at a time subsequent to the stress time period, the gate test voltage to the gate and the drain test voltage to the drain of the MOSFET and measuring a test current flow in the drain;

wherein if the test current flow differs from the initial current flow by less than a first selected amount, the wafer passes the hot-carrier injection screen, and

wherein the drain test voltage is less than the threshold voltage.

2. The method as recited in claim 1, wherein, if the test current flow differs from the initial current flow by greater than the first selected amount, then the screening method further comprises the steps of:

e) repeating steps c) and d) for successively longer test time periods until an accumulated stress time is met or exceeded, or the test current flow differs from the initial current flow by greater than a second selected amount, the second selected amount being greater than the first selected amount;

wherein if the accumulated stress time is met or exceeded without the test current flow differing from the initial current flow by greater than the second selected amount, the wafer passes the hot-carrier injection screen.

3. The method as recited in claim 2, wherein, the wafer passes the hot-carrier injection test in step e) if the test current flow differs from the initial current flow by less than the second selected amount.

4. The method as recited in claim 2, wherein the first and second selected amounts are expressed in a percent change and the second selected amount is approximately 4%.

5. The method as recited in claim 4, wherein first selected amount is approximately 3%.

6. The method as recited in claim 1, wherein the gate stress voltage is substantially equal to the drain stress voltage.

7. The method as recited in claim 1, wherein the gate stress voltage is less than the drain stress voltage.

8. The method as recited in claim 1, wherein the MOSFET has a design voltage, the gate test voltage is approximately equal to the design voltage of the MOSFET, and the gate stress voltage and drain stress voltage are substantially equal and are greater than the design voltage.

9. The method as recited in claim 8, wherein the stress voltages are approximately the 1.5 times the design voltage.

10. A method of hot-carrier injection screening a plurality of wafers, the method comprising:

a) selecting one wafer from the plurality of wafers, each wafer having a plurality of MOSFETs thereon and each of the MOSFETs having at least a gate, a drain, and a threshold voltage;

b) selecting one of the plurality of MOSFETs on the selected wafer;

c) applying a gate test voltage to the gate of the selected MOSFET and a drain test voltage to the drain of the selected MOSFET and measuring an initial current flow in the drain of the selected MOSFET;

d) applying, during a stress time period, a gate stress voltage to the gate of the selected MOSFET and a drain stress voltage to the drain of the selected MOSFET;

e) applying, at a time subsequent to the stress time period, the gate test voltage to the gate and the drain test voltage to the drain of the selected MOSFET and measuring a test current flow in the drain of the selected MOSFET;

f) adjusting at least one of the gate and drain stress voltages if the test current flow differs from the initial current flow by less than a selected minimum amount or more than a selected maximum amount;

g) repeating steps c) through f) with another MOSFET selected from the plurality of MOSFETs until the test current flow differs from the initial current flow greater than the selected minimum amount and less than the selected maximum amount; and

h) hot-carrier injection testing at least one of the remaining wafers of the plurality of wafers using the stress voltages determined in steps c) through g);

wherein the drain test voltage is less than the threshold voltage.

11. The method as recited in claim 10, wherein in step f), the gate and drain stress voltages are substantially equal and the stress voltages are adjusted by incrementing the stress voltages in substantially equal steps if the test current flow differs from the initial current flow by less than the selected minimum amount, or the stress voltages are adjusted by decrementing the voltages in substantially equal steps if the test current flow differs from the initial current flow by more than the selected maximum amount.

12. The method as recited in claim 10, wherein step h) further comprises the steps of:

h1) selecting another wafer from the plurality of wafers, the another wafer having at least one MOSFET thereon, the MOSFET having at least a gate and a drain;

h2) measuring an initial current flow in the drain while the gate test voltage is applied to the gate and the drain test voltage is applied to the drain of the MOSFET of the another wafer;

h3) applying, during a stress time period, the gate stress voltage to the gate and the drain stress voltage to the drain of the MOSFET of the another wafer; and

h4) applying, at a time subsequent to the stress time period, the gate test voltage to the gate and the drain test voltage to the drain of the MOSFET of the another wafer and measuring a test current flow in the drain of the MOSFET of the another wafer;

wherein if the test current flow differs from the initial current flow by less than a first selected amount, the another wafer passes the hot-carrier screen.

13. The method as recited in claim 12, wherein, if the test current flow in step h4) differs from the initial current flow in step h2) by greater than the first selected amount then the screening method further comprises the steps of:

i) repeating steps h3) and h4) for successively longer stress time periods until a maximum accumulated stress time is approximately met or the test current flow differs from the initial current flow by greater than second selected amount, the second selected amount being greater than the first selected amount.

14. The method as recited in claim 13, wherein, the another wafer passes the hot-carrier screen if the test current flow differs from the initial current flow by less than the second selected amount in step i).

15. The method as recited in claim 14, wherein the first and second selected amounts are expressed in a percent change and the first and second selected amounts are approximately 3% and 4%, respectively.

16. The method as recited in claim 13, wherein the selected MOSFET and the MOSFET of the another wafer have substantially equal design voltages and a threshold voltages, the gate test voltage is approximately the design voltage, the drain test voltage is less than the threshold voltage, and the gate and drain stress voltages are substantially the same and greater than the design voltage.

17. The method as recited in claim 10, wherein the gate stress voltage is less than the drain stress voltage.

18. The method as recited in claim 10, wherein the drain test voltage is less than the threshold voltage of the selected MOSFET.

19. A method of hot-carrier screening a plurality of wafers, the method comprising:

a) selecting one wafer from the plurality of wafers, each wafer having a plurality of MOSFETs thereon and each of the MOSFETs having at least a gate, a drain, and a threshold voltage;

b) selecting one of the plurality of MOSFETs on the selected wafer;

c) applying a gate test voltage to the gate of the selected MOSFET and a drain test voltage to the drain of the selected MOSFET and measuring an initial current flow in the drain of the selected MOSFET;

d) applying, during a stress time period, a stress voltage to the gate and drain of the selected MOSFET;

e) applying, at a time subsequent to the stress time period, the gate test voltage to the gate and the drain test voltage to the drain of the selected MOSFET and measuring a test current flow in the drain of the selected MOSFET;

f) adjusting the stress voltage if the test current flow differs from the initial current flow by less than a selected minimum amount or more than a selected maximum amount;

g) repeating steps c) through f) with another MOSFET selected from the plurality of MOSFETs until the test current flow differs from the initial current flow is as much or more than the selected minimum amount and as much or less than the selected maximum amount;

h) selecting another wafer from the plurality of wafers, the another wafer having at least one MOSFET thereon, the MOSFET having at least a gate and a drain;

i) applying the gate test voltage to the gate and the drain test voltage to the drain of the MOSFET of the another wafer and measuring an initial current flow in the drain;

j) applying, during a stress time period, the adjusted stress voltage to the gate and the drain of the MOSFET of the another wafer; and

k) applying, at a time subsequent to the stress time period in step j), the gate test voltage to the gate and the drain test voltage to the drain of the MOSFET of the another wafer and measuring a test current flow in the drain of the MOSFET of the another wafer;

wherein the drain test voltage being less than the threshold voltage,

wherein, in step f), the adjusted stress voltages are adjusted by incrementing the voltages in substantially equal steps if the test current flow differs from the initial current flow by less than the selected minimum amount, or the stress voltages are adjusted by decrementing the voltages in substantially equal steps if the test current flow differs from the initial current flow by more than the selected maximum amount, and

wherein if the test current flow measured in step k) differs from the initial current flow measured in step i) by less than a first selected amount, the another wafer passes the hot-carrier screen.

20. The method as recited in claim 19, wherein the selected MOSFET and the MOSFET of the another wafer have substantially equal design voltages and a threshold voltages, the gate test voltage is approximately the design voltage, the drain test voltage is less than the threshold voltage, and the adjusted stress voltage is greater than the design voltage.