LATCH AND DFF DESIGN WITH IMPROVED SOFT ERROR RATE AND A METHOD OF OPERATING A DFF

• US 20100156494A1
• Filed: 12/18/2008
• Published: 06/24/2010
• Est. Priority Date: 12/18/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Turner, Mark F., Brown, Jeff S.
• Granted Patent: US 7,932,762 B2
• Time in Patent Office: Days
• US Class Current: 327/202
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence
• CPC Class Codes: H03K 3/356147 using pass gates
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors

Abstract

A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a feedback path coupled to the passgate, the data output coupled thereto and (3) tristate circuitry coupled to the passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, the Boolean logic gates configured to control operation of the single transistor pair based on the data input and a pulse clock signal to drive the feedbacks path.

Claims

1. A latch having a data input and a data output, comprising:

a passgate coupled to said data input;

a feedback path coupled to said passgate, said data output coupled thereto; and

tristate circuitry coupled to said passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, said Boolean logic gates configured to control operation of said single transistor pair based on said data input and a pulse clock signal to drive said feedback path.

2. The latch as recited in claim 1 wherein said Boolean logic gates include a single NAND gate and a single NOR gate.

3. The latch as recited in claim 2 wherein a first input of said NAND gate is coupled to a positive clock pulse signal of said pulse clock signal and a first input of said NOR gate is coupled to a negative clock pulse signal of said pulse clock signal.

4. The latch as recited in claim 3 wherein said single transistor pair includes a PMOS transistor and an NMOS transistor, said PMOS transistor coupled to and controlled by said NAND gate and said NMOS transistor coupled to and controlled by said NOR gate.

5. The latch as recited in claim 4 further comprising another passgate, a feedback driver and another feedback path coupled between said feedback driver and said another passgate.

6. The latch as recited in claim 5 wherein said feedback driver is coupled to said tristate circuitry and configured to drive said another feedback path.

7. The latch as recited in claim 2 wherein said NAND gate includes only three transistors and said NOR gate includes only three transistors.

8. A method of operating a D flip-flop having a data input and a data output, comprising:

receiving a logic state into a master stage via a passgate thereof, said master stage further including master stage tristate circuitry having a single transistor pair of opposite conductivity coupled to master stage Boolean logic gates;

passing said logic state from said master stage to a slave stage via a slave stage passgate coupled to said master stage; and

passing said logic state from said slave stage passgate to said data output via said slave stage having tristate circuitry, said slave stage tristate circuitry having a slave stage single transistor pair of opposite conductivity coupled to slave stage Boolean logic gates.

9. The method as recited in claim 8 further comprising:

controlling operation of said master stage single transistor pair by said master stage Boolean logic gates based on said logic state received from said master stage passgate and said pulse clock signal.

10. The method as recited in claim 9 further comprising driving a first feedback path of said master stage coupled between said master stage single transistor pair and said master stage passgate employing said master stage single transistor pair.

11. The method as recited in claim 10 further comprising:

controlling operation of said slave stage single transistor pair by said slave stage Boolean logic gates based on said logic state received from said slave stage passgate and said pulse clock signal.

12. The method as recited in claim 11 further comprising driving a first feedback path of said slave stage coupled between said slave stage single transistor pair and said slave stage passgate employing said slave stage single transistor pair.

13. The method as recited in claim 12 wherein said master stage and slave stage both further include another passgate, a feedback driver and another feedback path coupled between said feedback driver and said another passgate.

14. The method as recited in claim 13 further comprising driving said another feedback path in said master stage and said slave stage employing each of said respective feedback drivers.

15. A D flip-flop having a data input and a data output and comprising:

a master stage having a master stage passgate coupled to said data input and a slave stage having a slave stage passgate coupled to said master stage, wherein both of said master stage and said slave stage include;

a feedback path; and

tristate circuitry coupled to said feedback path and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, said Boolean logic gates configured to control operation of said single transistor pair based on said data input and a pulse clock signal to drive said feedback path.

16. The D flip-flop as recited in claim 15 wherein said Boolean logic gates include a single NAND gate and a single NOR gate.

17. The D flip-flop as recited in claim 16 wherein a first input of said NAND gate is coupled to a positive clock pulse signal of said pulse clock signal and a first input of said NOR gate is coupled to a negative clock pulse signal of said pulse clock signal.

18. The D flip-flop as recited in claim 17 wherein said single transistor pair includes a PMOS transistor and an NMOS transistor, said PMOS transistor coupled to and controlled by said NAND gate and said NMOS transistor coupled to and controlled by said NOR gate.

19. The D flip-flop as recited in claim 18 further comprising another passgate, a feedback driver and another feedback path coupled between said feedback driver and said another passgate.

20. The D flip-flop as recited in claim 19 said feedback driver is coupled to said tristate circuitry and configured to drive said another feedback path.

21. The D flip-flop as recited in claim 16 wherein said NAND gate includes only three transistors and said NOR gate includes only three transistors.

22. A library of standard logic elements, comprising:

a standard logic element corresponding to a single-path latch having;

a passgate configured to receive a data input;

a feedback path coupled to said passgate and an output of said single-path latch; and

tristate circuitry coupled to said passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, said Boolean logic gates configured to control operation of said single transistor pair based on said data input and a pulse clock signal to drive said feedback path.

23. The library as recited in claim 22 further comprising a standard logic element corresponding to a dual-path latch having:

two passgates configured to receive a data input;

two different feedback paths coupled to said passgates;

tristate circuitry coupled to said passgates and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, said Boolean logic gates configured to control operation of said single transistor pair based on said data input and a pulse clock signal to drive at least one of said two feedback paths; and

a feedback driver coupled to said tristate circuitry and configured to drive only one of said two feedback paths.

24. The library as recited in claim 23 further comprising a standard logic element corresponding to a D flip-flop having one of said dual-path latch as a master stage and having another one of said dual-path latch as a slave stage.

25. The library as recited in claim 22 further comprising a standard logic element corresponding to a D flip-flop having one of said single-path latch as a master stage and having another one of said single-path latch as a slave stage.

26. The library as recited in claim 23 further comprising a standard logic element corresponding to a NAND gate having only three transistors and a standard logic element corresponding to a NOR gate having only three transistors.

27. The library as recited in claim 26 further comprising a standard logic element employing said NAND gate and said NOR gate.