SAR ANALOG-TO-DIGITAL CONVERTER HAVING VARIABLE CURRENTS FOR LOW POWER MODE OF OPERATION
First Claim
1. A successive approximation register (SAR) analog-to-digital converter (ADC), comprisinga capacitor array including a plurality of switched capacitors therein with varying weights each having a common plate connected to a common node and a switched plate;
- at least one comparator for comparing the voltage on the common node of the capacitor array with a reference voltage, the at least one comparator having a first bias voltage current applied thereto;
a SAR controller for sampling an input voltage on said capacitor array in a sampling phase, and redistributing the charge stored thereon in a conversion phase by selectively changing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm;
wherein the first bias current operates at first levels responsive to a first mode of operation of the SAR ADC and operates at second levels responsive to a second mode of operation of the SAR ADC; and
wherein the common node is connected to said common mode voltage, and the switched plate is connectable to the input voltage during the sampling phase, and during the conversion phase, the switched plate of each of said array capacitors are connectable to the reference voltage to redistribute the charge thereon to the array and change the voltage on the common node.
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Accused Products
Abstract
A successive approximation analog-to-digital converter includes a capacitor array having a plurality of switch capacitors therein with varying weights, each having a common plate connected to a common node and a switched plate. A SAR controller samples an input voltage on said capacitor array in a sampling phase and redistributes the charge stored therein in a conversion phase by selectively increasing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm. Circuitry controls the sampling of the input voltage by the capacitor array and is responsive to at least one applied bias current. The at least one applied bias current operates at a first level responsive to a first mode of operation of the SAR ADC and operates at a second level responsive to a second mode of operation of the SARADC.
25 Citations
18 Claims
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1. A successive approximation register (SAR) analog-to-digital converter (ADC), comprising
a capacitor array including a plurality of switched capacitors therein with varying weights each having a common plate connected to a common node and a switched plate; -
at least one comparator for comparing the voltage on the common node of the capacitor array with a reference voltage, the at least one comparator having a first bias voltage current applied thereto; a SAR controller for sampling an input voltage on said capacitor array in a sampling phase, and redistributing the charge stored thereon in a conversion phase by selectively changing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm; wherein the first bias current operates at first levels responsive to a first mode of operation of the SAR ADC and operates at second levels responsive to a second mode of operation of the SAR ADC; and wherein the common node is connected to said common mode voltage, and the switched plate is connectable to the input voltage during the sampling phase, and during the conversion phase, the switched plate of each of said array capacitors are connectable to the reference voltage to redistribute the charge thereon to the array and change the voltage on the common node. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A successive approximation register (SAR) analog-to-digital converter (ADC), comprising:
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a capacitor array including a plurality of switched capacitors therein with varying weights each having a common plate connected to a common node and a switched plate; a SAR controller for sampling an input voltage on said capacitor array in a sampling phase, and redistributing the charge stored thereon in a conversion phase by selectively changing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm; circuitry for controlling the sampling of the input voltage by the capacitor array, the circuitry for controlling operating responsive to at least one applied bias current, wherein the at least one applied bias current operates at first levels responsive to a first mode of operation of the SAR ADC and the at least one applied bias current operates at second levels responsive to a second mode of operation of the SAR ADC. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method for saving power within a successive approximation register (SAR) analog-to-digital converter (ADC), comprising the steps of:
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monitoring an operating frequency of the SAR ADC; generating an output current responsive to the monitored operating frequency of the SAR ADC, wherein the output current operates at a first level responsive to a first operating frequency of the SAR ADC and operates at a second level responsive to a second operating frequency of the SAR ADC; and providing a bias current to at least one component of the SAR ADC at a third level responsive to the output current at a first level and at a fourth level responsive to the output current at the second level. - View Dependent Claims (15, 16, 17, 18)
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Specification