IMAGE PROCESSING APPARATUS AND METHOD FOR MANAGING FRAME MEMORY IN IMAGE PROCESSING

• US 20100156917A1
• Filed: 10/15/2009
• Published: 06/24/2010
• Est. Priority Date: 12/22/2008
• Status: Abandoned Application

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Lee, Suk Ho, Lee, Sang Heon, LEE, Hoo Sung, Kim, Ig Kyun, Park, Seong Mo, Eum, Nak Woong, Shin, Kyoung Seon
• Application Number:
  US12/579,630
• Publication Number:
  US 20100156917A1
• Time in Patent Office: Days
• US Class Current: 345/543
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence

Abstract

A method for managing a frame memory includes: determining a frame memory structure with reference to memory configuration information and image processing information; configuring a frame memory such that a plurality of image signals are stored in each page according to the frame memory structure; and computing a signal storage address by combining image acquiring information by bits, and accessing a frame memory map to write or read an image signal by pages.

Claims

1. A method for managing a frame memory, the method comprising:

determining a frame memory structure with reference to memory configuration information and image processing information;

configuring a frame memory such that a plurality of image signals are stored in each page according to the frame memory structure; and

computing signal storage addresses by combining image acquiring information by bits, and accessing a frame memory map to write or read an image signal by pages.

2. The method of claim 1, wherein, in determining the frame memory structure, the maximum number of frames of the frame memory, the number of image lines per page, a frame offset, and a chrominance signal offset are determined with reference to the memory configuration information including information about a page size, a bus width, the number of banks, and the number or rows, and the image processing information including information about a width and height of an image.

3. The method of claim 2, wherein, in determining the frame memory structure, the maximum number of frames and the number of image lines per page are determined by equations shown below:

Image width=pixel width of a macroblock unit×

16  

 

1)

Image height=pixel height of a macroblock unit×

16  

 

2)

Frame access line distance=2^{(Ceil(log2(image width)))}  

 

3)

Field access line distance=frame access line distance×

2  

 

4)

Number of image lines per page=page size/frame access line distance  

 

5)

Maximum number of frames=floor(number of memory rows/frame offset)  

 

6)

wherein ceil a round-up value and the floor is a round-down value.

4. The method of claim 2, wherein, in determining the frame memory structure, the frame offset and the chrominance signal offset are determined according to equation shown below or is inputted by a user:

chrominance signal offset=image height/image lines per page/number of banks,  

 

(1)

frame offset=chrominance offset×

3/2.  

 

(2)

5. The method of claim 2, wherein, in configuring the frame memory, the number of frames is determined according to the maximum number of frames, a single bank is divided into a plurality of subbanks according to the number of image lines per page, and a luminance signal and a chrominance signal are separately stored according to the frame offset and the chrominance signal offset.

6. The method of claim 5, wherein, in configuring the frame memory, when an image signal includes a luminance signal and first and second chrominance signals, a start address of rows for storing the luminance signal is determined according to the frame offset, and a start address of rows for storing the first and second chrominance signals is determined according to the frame offset and the chrominance signal offset.

7. The method of claim 5, wherein, in configuring the frame memory, when an image signal includes a luminance signal and first and second chrominance signals, a plurality of luminance signals or the first and second chrominance signals are stored together in a single page.

8. The method of claim 1, wherein, in writing and reading, when an image signal includes a luminance signal and first and second chrominance signals and a frame offset is 2n, a luminance signal address and first and second chrominance signal addresses are acquired from image acquisition information including a frame index, a signal type, and x and Y coordinates according to equations shown below:

a luminance pixel address={frame index,luminance pixel, Y coordinate, X coordinate}={row address, bank address, column address, byte address},  

 

1)

first chrominance pixel address={frame index, chrominance pixel, Y coordinate, X coordinate, a chrominance pixel type}={row address, bank address, column address, byte address}, and  

 

2)

second chrominance pixel address=first chrominance pixel address+1.  

 

3)

9. The method of claim 1, in writing and reading, when an image signal includes a luminance signal and first and second chrominance signals and a frame offset is not 2n, a luminance signal address and first and second chrominance signal addresses are acquired from image acquisition information including a frame index, a signal type, and x and Y coordinates, according to equations shown below:

a luminance pixel address=frame index×

frame offset+{Y coordinate, X coordinate}={row address, bank address, column address, byte address},  

 

1)

first chrominance pixel address=frame index×

frame offset+chrominance offset+{Y coordinate>

>

1, X coordinate>

>

1, a chrominance pixel type}={row address, bank address, column address, byte address}, and  

 

2)

second chrominance pixel address=first chrominance pixel address+1.  

 

3)

10. The method of claim 1, wherein, in writing and reading, accessing is performed in a bank interleaving manner, and in this case, an access unit is changed by correcting a line distance.

11. The method of claim 10, wherein, in writing and reading, a field access line distance is double a frame access line distance.

12. An apparatus for managing a frame memory, the apparatus comprising:

a stream controller that interprets an image data stream provided from a host system;

a stream processing unit that reads an image signal of a region corresponding to a motion vector provided from the stream controller, from a frame memory to configure a motion compensation screen image, and configures a predicted screen image and a residual screen image based on data provided from the stream controller;

a screen image reconfiguring unit that configures an original screen image by adding the predicted screen image or the motion compensation screen image and the residual screen image in a screen image;

a deblocking filter that reads a screen image of a neighbor block from the frame memory, filters the read screen image together with the original screen image, and restores the same in the frame memory; and

a frame memory controller that provides control to simultaneously store a plurality of image signals in each page of the frame memory, and acquires a signal storage address from image acquisition information through a bit unit combining method and accesses the frame memory to write or read an image signal by pages when the stream processing unit or the deblocking filter requests accessing.

13. The apparatus of claim 12, wherein the frame memory controller determines the maximum number of frames of the frame memory, the number of image lines per page, a frame offset, and a chrominance signal offset with reference to the memory configuration information including information about a page size, a bus width, the number of banks, and the number or rows, and the image processing information including information about a width and height of an image.

14. The apparatus of claim 13, wherein the frame memory controller determines the number of frames according to the maximum number of frames, divides a single bank into a plurality of subbanks according to the number of image lines per page, and separately stores a luminance signal and a chrominance signal according to a frame offset and a chrominance signal offset.

15. The apparatus of claim 13, wherein when an image signal includes a luminance signal and first and second chrominance signals and a frame offset is 2n, the frame memory controller acquires a luminance signal address and first and second chrominance signal addresses from image acquisition information including a frame index, a signal type, and x and Y coordinates, according to the following equations:

a luminance pixel address={frame index, luminance pixel, Y coordinate, X coordinate}={row address, bank address, column address, byte address},  

 

1)

first chrominance pixel address={frame index, chrominance pixel, Y coordinate, X coordinate, a chrominance pixel type}={row address, bank address, column address, byte address}, and  

 

2)

second chrominance pixel address=first chrominance pixel address+1.  

 

3)

16. The apparatus of claim 13, when an image signal includes a luminance signal and first and second chrominance signals and a frame offset is not 2n, the frame memory controller acquires a luminance signal address and first and second chrominance signal addresses from image acquisition information including a frame index, a signal type, and x and Y coordinates, according to the following equations:

a luminance pixel address=frame index×

frame offset+{Y coordinate, X coordinate}={row address, bank address, column address, byte address},  

 

1)

first chrominance pixel address=frame index×

frame offset+chrominance offset+{Y coordinate>

>

1, X coordinate>

>

1, a chrominance pixel type}={row address, bank address, column address, byte address}, and  

 

2)

second chrominance pixel address=first chrominance pixel address+1.  

 

3)

17. The apparatus of claim 13, wherein the frame memory controller performs accessing in a bank interleaving manner, and in this case, an access unit is changed by correcting a line distance.

18. The apparatus of claim 17, wherein a field access line distance is double a frame access line distance.