ARC FAULT CIRCUIT INTERRUPTER AND METHOD PROVIDING IMPROVED NUISANCE TRIP REJECTION

• US 20100157486A1
• Filed: 12/19/2008
• Published: 06/24/2010
• Est. Priority Date: 12/19/2008
• Status: Active Grant

• Current Assignee: Eaton Intelligent Power Limited (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Miller, Theodore J., Parker, Kevin L.
• Granted Patent: US 8,089,737 B2
• Time in Patent Office: Days
• US Class Current: 361/2
• CPC Class Codes: H02H 1/0015 Using arc detectors
• CPC Class Codes: H02H 1/0092 concerning the data processing means, e.g. expert systems, neural networks

Abstract

An arc fault circuit interrupter includes separable contacts, an operating mechanism and an arc fault detector structured to detect an arc fault condition operatively associated with the contacts. The arc fault detector includes a tuned current sensor structured to sense broadband noise of a current flowing through the contacts, a compression circuit including an input of the sensed broadband noise and an output. The compression circuit compresses the dynamic range of the sensed broadband noise. A minimum detector includes an input of the compression circuit output and an output of the minimum value of the minimum detector input. A processor includes a number of inputs and an output. One of the inputs is the output of the minimum value of the minimum detector. A trip mechanism cooperates with the output of the processor and the operating mechanism to trip open the contacts responsive to the detected arc fault condition.

Claims

1. An arc fault circuit interrupter comprising:

separable contacts;

an operating mechanism structured to open and close said separable contacts;

an arc fault detector structured to detect an arc fault condition operatively associated with said separable contacts, said arc fault detector comprising;

a tuned current sensor structured to sense broadband noise of a current flowing through said separable contacts,

a compression circuit including an input of said sensed broadband noise from said tuned current sensor and an output, said compression circuit being structured to compress the dynamic range of said sensed broadband noise,

a minimum detector including an input of the output of said compression circuit and an output of the minimum value of said input of said minimum detector, and

a processor including a number of inputs and an output, one of said number of inputs being the output of the minimum value of said minimum detector; and

a trip mechanism cooperating with the output of said processor and said operating mechanism to trip open said separable contacts responsive to said detected arc fault condition.

2. The arc fault circuit interrupter of claim 1 wherein said tuned current sensor is structured to output said sensed broadband noise.

3. The arc fault circuit interrupter of claim 2 wherein said tuned current sensor is a current transformer structured to resonate at about 15 MHz.

4. The arc fault circuit interrupter of claim 1 wherein said compression circuit is a demodulating logarithmic amplifier structured to rectify said sensed broadband noise and perform a logarithmic conversion of the amplitude of said rectified sensed broadband noise.

5. The arc fault circuit interrupter of claim 1 wherein said processor is structured to periodically input the output of said minimum detector.

6. The arc fault circuit interrupter of claim 5 wherein said processor is further structured to input the output of said minimum detector synchronous with an alternating current half-cycle, compare a profile of the output of said minimum detector versus phase angle of said alternating current half-cycle against a plurality of profiles operatively associated with series arcs, and determine whether each alternating current half-cycle corresponds to one of said plurality of profiles.

7. The arc fault circuit interrupter of claim 1 wherein said minimum detector is structured to reject discretely spaced, high frequency pulses of said sensed broadband noise.

8. The arc fault circuit interrupter of claim 7 wherein said discretely spaced, high frequency pulses of said sensed broadband noise are generated by one of a universal motor and a power supply.

9. The arc fault circuit interrupter of claim 7 wherein said minimum detector is structured to pass high frequency pulses of said sensed broadband noise from said arc fault condition.

10. The arc fault circuit interrupter of claim 1 wherein said arc fault detector further comprises a line current sensor including an output structured to output a signal proportional to line current;

and wherein one of said number of inputs of said processor is the output of said line current sensor.

11. The arc fault circuit interrupter of claim 10 wherein said arc fault detector further comprises a line voltage zero crossing detector structured to synchronize said processor with a line voltage.

12. The arc fault circuit interrupter of claim 1 wherein said processor comprises an analog-to-digital converter structured to input and convert the output of said minimum detector.

13. The arc fault circuit interrupter of claim 1 wherein the output of said minimum detector is proportional to the minimum of the logarithm of the envelope of said sensed broadband noise;

wherein the output of said minimum detector is structured to increase in response to continuous broadband noise from said arc fault condition; and

wherein the output of said minimum detector is structured to not increase in response to non-continuous broadband noise.

14. The arc fault circuit interrupter of claim 1 wherein said processor is structured to determine if a predetermined number of alternating current half-cycles indicates series arcing occurring within a predetermined time interval, and to responsively set the output of said processor to responsively trip open said separable contacts.

15. The arc fault circuit interrupter of claim 1 wherein said arc fault detector further comprises a zero crossing detector structured to synchronize said processor with a plurality of line half-cycles;

and wherein said processor comprises an analog-to-digital converter structured to input and convert the output of said minimum detector, and a routine structured to input and reset the output of said minimum detector a plurality of times for each of said line half-cycles.

16. The arc fault circuit interrupter of claim 15 wherein said processor comprises a routine structured to determine a minimum value from the output of said minimum detector for each of said line half-cycles, a maximum value from the output of said minimum detector for each of said line half-cycles, a dynamic range value from the difference between said maximum value and said minimum value, a count of a number of the outputs of said minimum detector that exceed a first predetermined value for each of said line half-cycles, and a condition defined by:

(a) said dynamic range value being greater than a second predetermined value, (b) said minimum value occurs at one of either a plurality of the outputs of said minimum detector at the beginning of a corresponding one of said line half-cycles or a plurality of the outputs of said minimum detector at the end of the corresponding one of said line half-cycles, and (c) said count of the number of the outputs of said minimum detector that exceed the first predetermined value being greater than a third predetermined value.

17. The arc fault circuit interrupter of claim 16 wherein the routine of said processor is further structured to input 32 samples of the outputs of said minimum detector for each of said line half-cycles;

wherein said plurality of the outputs of said minimum detector at the beginning of the corresponding one of said line half-cycles are about the first five of said 32 samples; and

wherein said plurality of the outputs of said minimum detector at the end of the corresponding one of said line half-cycles are about the last five of said 32 samples.

18. The arc fault circuit interrupter of claim 16 wherein the routine of said processor is further structured to input 32 samples of the outputs of said minimum detector for each of said line half-cycles;

wherein said plurality of the outputs of said minimum detector at the beginning of the corresponding one of said line half-cycles are about the first three of said 32 samples; and

wherein said plurality of the outputs of said minimum detector at the end of the corresponding one of said line half-cycles are about the last two of said 32 samples.

19. The arc fault circuit interrupter of claim 1 wherein said processor comprises a routine structured to determine a minimum value from the output of said minimum detector for each of said line half-cycles, a maximum value from the output of said minimum detector for each of said line half-cycles, a dynamic range value from the difference between said maximum value and said minimum value, a maximum difference between subsequent values from the output of said minimum detector for each of said line half-cycles, a count of a number of the outputs of said minimum detector that are less than a first predetermined value for each of said line half-cycles plus a number of the outputs of said minimum detector that are greater than a second predetermined value for each of said line half-cycles, and a condition defined by:

(a) said dynamic range value being greater than a third predetermined value, (b) the last said count being greater than a fourth predetermined value, (c) said maximum difference being greater than a fifth predetermined value, (d) said maximum difference occurs after a first sample at the beginning of a corresponding one of said line half-cycles, and (e) said maximum difference occurs before a plurality of samples at the end of the corresponding one of said line half-cycles.

20. The arc fault circuit interrupter of claim 19 wherein the routine of said processor is further structured to input 32 samples of the outputs of said minimum detector for each of said line half-cycles;

and wherein said maximum value occurs before about the 25^th one of said 32 samples at the end of the corresponding one of said line half-cycles.

21. The arc fault circuit interrupter of claim 19 wherein the routine of said processor is further structured to input and reset the output of said minimum detector a plurality of times for each of a plurality of line half-cycles, determine a maximum change value between adjacent pairs of the output of said minimum detector for said plurality of times for each of said plurality of line half-cycles, a position value corresponding to the maximum change value for one of said plurality of times, and a condition defined by:

(a) said dynamic range value being greater than a sixth predetermined value, (b) said maximum change value being greater than a seventh predetermined value, (c) said position value being greater than an eighth predetermined value and being less than a ninth predetermined value, and (d) said count being greater than a tenth predetermined value.

22. The arc fault circuit interrupter of claim 15 wherein said processor comprises a routine structured to determine a minimum value from the output of said minimum detector for each of said line half-cycles, a maximum value from the output of said minimum detector for each of said line half-cycles, a dynamic range value from the difference between said maximum value and said minimum value, a count of a number of the outputs of said minimum detector that either exceed a first predetermined value for each of said line half-cycles or that are less than a second predetermined value for each of said line half-cycles, a maximum change value between adjacent pairs of the output of said minimum detector for the plurality of times for each of said line half-cycles, a position value corresponding to the maximum change value for one of said plurality of times, and a condition defined by:

(a) said dynamic range value being greater than a third predetermined value, (b) said maximum change value being greater than a fourth predetermined value, (c) said position value being greater than a fifth predetermined value and being less than a sixth predetermined value, and (d) said count being greater than a seventh predetermined value.

23. A method of detecting an arc fault condition of an alternating current power circuit having a plurality of half-cycles, said method comprising:

sensing broadband noise of a current flowing in said power circuit;

compressing the dynamic range of said sensed broadband noise;

detecting a minimum of said compressed and sensed broadband noise for a plurality of samples for each of said half-cycles;

determining a minimum value from said minimum of the compressed and sensed broadband noise for said samples for each of said half-cycles;

determining a maximum value from said minimum of the compressed and sensed broadband noise for said samples for each of said half-cycles;

determining a dynamic range value from the difference between said maximum value and said minimum value;

determining a count of a number of said samples that exceed a first predetermined value for each of said line half-cycles;

determining a condition defined by;

(a) said dynamic range value being greater than a second predetermined value, (b) said minimum value occurs at one of either a plurality of the samples at the beginning of a corresponding one of said line half-cycles or a plurality of the samples at the end of the corresponding one of said line half-cycles, and (c) said count of the number of the samples that exceed the first predetermined value being greater than a third predetermined value;

increasing an accumulator responsive to said condition being met or decreasing said accumulator responsive to said condition not being met; and

detecting said arc fault condition when said accumulator exceeds a fourth predetermined value.

24. A method of detecting an arc fault condition of an alternating current power circuit having a plurality of half-cycles, said method comprising:

sensing broadband noise of a current flowing in said power circuit;

compressing the dynamic range of said sensed broadband noise;

detecting a minimum of said compressed and sensed broadband noise for a plurality of samples for each of said half-cycles;

determining a minimum value from said minimum of the compressed and sensed broadband noise for said samples for each of said half-cycles;

determining a maximum value from said minimum of the compressed and sensed broadband noise for said samples for each of said half-cycles;

determining a dynamic range value from the difference between said maximum value and said minimum value;

determining a maximum difference between subsequent values from said minimum of the compressed and sensed broadband noise for each of said line half-cycles;

determining a count of a number of said minimum of the compressed and sensed broadband noise that are less than a first predetermined value for each of said line half-cycles plus a number of said minimum of the compressed and sensed broadband noise that are greater than a second predetermined value for each of said line half-cycles;

determining a condition defined by;

(a) said dynamic range value being greater than a third predetermined value, (b) the last said count being greater than a fourth predetermined value, (c) said maximum difference being greater than a fifth predetermined value, (d) said maximum difference occurs after a first sample at the beginning of a corresponding one of said line half-cycles, and (e) said maximum difference occurs before a plurality of samples at the end of the corresponding one of said line half-cycles;

increasing an accumulator responsive to said condition being met or decreasing said accumulator responsive to said condition not being met; and

detecting said arc fault condition when said accumulator exceeds a sixth predetermined value.