Digital potentiometer using third dimensional memory

• US 20100157659A1
• Filed: 12/18/2009
• Published: 06/24/2010
• Est. Priority Date: 12/22/2008
• Status: Active Grant

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Norman, Robert
• Granted Patent: US 8,164,937 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03G 3/001 Digital control of analog signals
• CPC Class Codes: H03H 11/24 Frequency-independent attenuators

Abstract

A digital potentiometer using third dimensional memory includes a switch configured to electrically couple one or more resistive elements with a first pin and a second pin, and a non-volatile register configured to control the switch. In one example, the non-volatile register can include a BEOL non-volatile memory element, such as a third dimensional memory element. The non-volatile register can include a FEOL active circuitry portion that is electrically coupled with the BEOL non-volatile memory element to implement the non-volatile register. The resistive elements can be BEOL resistive elements that can be fabricated on the same plane or a different plane than the BEOL non-volatile memory elements. The BEOL non-volatile memory elements and the BEOL resistive elements can retain stored data in the absence of power and the stored data can be non-destructively determined by application of a read voltage.

Claims

1. A digital potentiometer, comprising:

a switch configured to electrically couple one or more resistive elements with a first pin and a second pin; and

a non-volatile register configured to control the switch, the non-volatile register including a portion of a back-end-of-the-line (BEOL) third dimensional memory.

2. The digital potentiometer of claim 1, wherein at least one of the resistive elements has an adjustable resistance.

3. The digital potentiometer of claim 1, wherein at least one of the resistive elements comprises a resistive memory element including a BEOL memory element, wherein a resistance of the BEOL memory element is adjustable as a function of a voltage differential across the BEOL memory element.

4. The digital potentiometer of claim 3, wherein the voltage differential is formed in association with multiple write signals.

5. The digital potentiometer of claim 3 and further comprising:

a front-end-of-the-line (FEOL) voltage generator circuit electrically coupled with the BEOL memory element and operative to generate the voltage differential using the multiple write signals.

6. The digital potentiometer of claim 1 and further comprising:

multiple layers of BEOL memory, one of the layers of BEOL memory including the portion of the BEOL third dimensional memory; and

a FEOL logic plane including the switch, the FEOL logic plane being disposed at a different layer than the portion of the BEOL third dimensional memory.

7. The digital potentiometer of claim 1, wherein a subset of the resistive elements are electrically coupled in series.

8. The digital potentiometer of claim 1, wherein a subset of the resistive elements are electrically coupled in parallel.

9. The digital potentiometer of claim 1, wherein a subset of the resistive elements are electrically coupled in series and another subset of the resistive elements are electrically coupled in parallel.

10. The digital potentiometer of claim 1, wherein the non-volatile register further comprises

a BEOL memory element including a first end and a second end and positioned in a first layer, and

a front-end-of-the-line (FEOL) register logic positioned in a second layer and electrically coupled with the first and second ends of the BEOL memory element, and

wherein the portion of the BEOL third dimensional memory includes the BEOL memory element.

11. A digital potentiometer, comprising:

a pin;

another pin;

a plurality of resistive elements;

a plurality of switches, at least one of the plurality of switches configured to electrically couple at least one of the plurality of resistive elements with the pin and the another pin; and

a non-volatile register that includes a portion of a back-end-of-the-line (BEOL) third dimensional memory, the non-volatile register configured to control the at least one of the plurality of switches.

12. The digital potentiometer of claim 11, wherein the plurality of switches are formed in a front-end-of-the-line (FEOL) plane positioned below and in contact with the BEOL third dimensional memory array and wherein at least a portion of the non-volatile register is formed in a first plane of the BEOL third dimensional memory array.

13. The digital potentiometer of claim 11, wherein at least one of the plurality of resistive elements has an adjustable resistance.

14. The digital potentiometer of claim 11, wherein at least one of the plurality of resistive elements is a resistive memory element including a BEOL memory element and a resistance of the BEOL memory element is adjustable as a function of a voltage differential across the BEOL memory element.

15. The digital potentiometer of claim 11, wherein the non-volatile register further comprises

a BEOL memory element including a first end and a second end and positioned in the BEOL third dimensional memory, and

a front-end-of-the-line (FEOL) register logic electrically coupled with the first and second ends of the BEOL memory element.

16. The digital potentiometer of claim 15, wherein the BEOL memory element and the FEOL register logic comprise a portion of a die.

17. The digital potentiometer of claim 16, wherein the BEOL memory element is formed in a first layer of the die and the FEOL register logic is formed in a base layer of the die.

18. The digital potentiometer of claim 15, wherein the BEOL memory element is formed in a BEOL non-volatile third dimensional memory array that includes one or more vertically-disposed layers that are positioned above a base layer for the FEOL register logic.

19. A digital potentiometer, comprising:

a plurality of resistive elements;

back-end-of-the-line (BEOL) non-volatile memory cells configured to select a subset of the plurality of resistive elements; and

a front-end-of-the-line (FEOL) configuration circuit configured to configure a subset of the BEOL non-volatile memory cells.

20. The digital potentiometer of claim 19, wherein the BEOL non-volatile memory cells are configured to select a subset of the plurality of resistive elements substantially at power-up.

21. The digital potentiometer of claim 19, wherein at least one of the plurality of resistive elements has an adjustable resistance.

22. The digital potentiometer of claim 19, wherein at least one of the plurality of resistive elements is a resistive memory element including a BEOL memory element, having an adjustable resistance that varies as a function of a voltage differential across the BEOL memory element.

23. The digital potentiometer of claim 19, wherein the plurality of resistive elements comprise BEOL resistive elements.

24. A method for programming a digital potentiometer, comprising:

configuring a plurality of non-volatile registers to select a resistance path including one or more resistive elements from a pin to another pin, each non-volatile register including a back-end-of-the-line (BEOL) non-volatile memory portion; and

applying a voltage differential to adjust the resistance of at least one of the one or more resistive elements.

25. The method of claim 24, wherein applying the voltage differential comprises, generating multiple write signals, and applying the multiple write signals to at least one memory plane in a plurality of BEOL memory planes.

26. The method of claim 25, wherein the multiple write signals comprises applying the multiple write signals to different memory planes in the plurality of BEOL memory planes, wherein a first BEOL memory plane includes the at least one of the one or more resistive elements.

27. The method of claim 24, wherein configuring the plurality of non-volatile registers comprises loading the plurality of non-volatile registers using a ring counter.

28. The method of claim 24, wherein configuring the plurality of non-volatile registers comprises loading the plurality of non-volatile registers using a decoder.

29. The method of claim 24, wherein the plurality of non-volatile registers includes a front-end-of-the-line (FEOL) active circuitry portion electrically coupled with the BEOL non-volatile memory portion, the BEOL non-volatile memory portion is vertically positioned above and in contact with the FEOL active circuitry portion.