Floating Gate Inverter Type Memory Cell And Array
First Claim
1. A non-volatile memory cell comprising:
- a control capacitor;
an inverter comprising a first inverter transistor and a second inverter transistor, wherein the control capacitor, the first inverter transistor and the second inverter transistor share a floating gate;
an output circuit comprising a first output transistor and a second output transistor, wherein the first output transistor and the first inverter transistor share a first common source/drain region, and the second output transistor and the second inverter transistor share a second common source/drain region.
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Abstract
A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell. In this case, the NMOS inverter transistor functions as a tunneling capacitor for programming and erasing the cell, and the PMOS inverter transistor functions as a tunneling capacitor for erasing the cell.
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Citations
23 Claims
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1. A non-volatile memory cell comprising:
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a control capacitor; an inverter comprising a first inverter transistor and a second inverter transistor, wherein the control capacitor, the first inverter transistor and the second inverter transistor share a floating gate; an output circuit comprising a first output transistor and a second output transistor, wherein the first output transistor and the first inverter transistor share a first common source/drain region, and the second output transistor and the second inverter transistor share a second common source/drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An array of non-volatile memory cells comprising:
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a first plurality of non-volatile memory cells that form a first row of the array, wherein each of the first plurality of non-volatile memory cells includes; a control capacitor having a corresponding floating gate electrode; an inverter that shares the floating gate electrode with the control capacitor; and an output circuit coupled to the inverter; wherein each control capacitor in the first row of the array shares a common first well region which forms a counter-electrode of the control capacitors in the first row. - View Dependent Claims (14, 15, 16, 17)
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18. A method of operating a non-volatile memory cell comprising:
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injecting electrons into a floating gate of the non-volatile memory cell by Fowler-Nordheim tunneling stimulated by voltage application to a control capacitor of the non-volatile memory cell; reading a state of the floating gate through a first inverter transistor and a first output transistor of the non-volatile memory cell, wherein the floating gate forms a gate of the first inverter transistor, and wherein the first inverter transistor and the first output transistor share a first common source/drain region in a substrate. - View Dependent Claims (19, 20, 21, 22, 23)
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Specification