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Floating Gate Inverter Type Memory Cell And Array

  • US 20100157669A1
  • Filed: 03/02/2010
  • Published: 06/24/2010
  • Est. Priority Date: 12/07/2006
  • Status: Active Grant
First Claim
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1. A non-volatile memory cell comprising:

  • a control capacitor;

    an inverter comprising a first inverter transistor and a second inverter transistor, wherein the control capacitor, the first inverter transistor and the second inverter transistor share a floating gate;

    an output circuit comprising a first output transistor and a second output transistor, wherein the first output transistor and the first inverter transistor share a first common source/drain region, and the second output transistor and the second inverter transistor share a second common source/drain region.

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