Method, Apparatus and System for Frequency Synchronization Between Devices Communicating over a Packet Network

• US 20100158051A1
• Filed: 12/19/2008
• Published: 06/24/2010
• Est. Priority Date: 12/19/2008
• Status: Active Grant

• Current Assignee: Piece Future Pte., Ltd.
• Original Assignee: Alcatel-Lucent SA (Nokia Corporation)
• Inventors: Hadzic, Ilija, Neustadt, Alf, Sayeed, Zulfiquar, Morgan, Dennis Raymond
• Granted Patent: US 8,300,749 B2
• Time in Patent Office: Days
• US Class Current: 370/503
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H04J 3/0664 unidirectional timestamps
• CPC Class Codes: H04J 3/0667 Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays arrangements for monitoring round trip delays in packet switching networks H04L43/0864

Abstract

An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop utilizes a frequency error estimator implemented as a maximum-likelihood estimator with slope fitting based on a sequence of arrival timestamps, and a loop filter implemented as a series combination of an adaptive-bandwidth filter and a proportional-integral controller. The clock recovery module may further comprise a discontinuity detector configured to detect a discontinuity in delays of respective timing messages, and a loop controller operative to place the clock recovery loop in a particular state responsive to detection of the discontinuity.

Claims

1. An apparatus comprising:

a communication device comprising a clock recovery module;

the communication device being operative as a slave device relative to another communication device that is operative as a master device;

the clock recovery module comprising a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device;

the clock recovery loop comprising;

a frequency error estimator configured to generate an estimate of error between the master clock frequency and the slave clock frequency; and

a loop filter;

wherein the frequency error estimator comprises a maximum-likelihood estimator with slope fitting based on a sequence of arrival timestamps generated in the slave device for respective timing messages received from the master device; and

wherein the loop filter comprises a series combination of an adaptive-bandwidth filter and a proportional-integral controller.

2. The apparatus of claim 1 wherein the maximum-likelihood estimator implements the slope fitting utilizing a linear regression technique.

3. The apparatus of claim 1 wherein the frequency error estimator comprises a finite impulse response filter having filter taps that update automatically in the event of gaps in the sequence of arrival timestamps due to missing timing messages.

4. The apparatus of claim 1 wherein the maximum-likelihood estimator generates the error estimate in accordance with the equation:

5. The apparatus of claim 1 wherein the adaptive-bandwidth filter of the clock recovery loop has a bandwidth that starts at a relatively wide value when the loop begins a convergence process and that subsequently narrows as the loop converges to a steady state.

6. The apparatus of claim 1 wherein the loop filter of the clock recovery loop has a transfer function given by:

7. The apparatus of claim 6 wherein the forgetting factor varies in the following manner as a function of phase error φ

_e of the clock recovery loop;

8. The apparatus of claim 1 wherein the adaptive-bandwidth filter has an adaptive gain which starts at a designated multiple of a nominal gain value, is reduced to a smaller multiple of the nominal gain value upon detection of a change in sign of the error estimate, and is subsequently further reduced to the nominal gain value.

9. The apparatus of claim 1 wherein the clock recovery module further comprises:

at least one discontinuity detector configured to detect a discontinuity in delays of respective ones of the timing messages; and

a loop controller operative to place the clock recovery loop in a particular state responsive to detection of the discontinuity.

10. The apparatus of claim 9 wherein the particular state comprises a holdover state in which a clock source used to generate the slave clock signal is not adjusted.

11. The apparatus of claim 9 wherein the detected discontinuity comprises a discontinuity involving at least one of a change in a floor of packet delay variation and a change in a variance of packet delay variation, wherein the floor is a minimum packet delay observed during a stationary interval of the packet delay variation that does not include the discontinuity.

12. The apparatus of claim 9 wherein the particular state comprises a previous state existing in the clock recovery loop prior to detection of the discontinuity.

13. The apparatus of claim 12 wherein the previous state corresponds to a state existing in the loop a designated number of samples prior to detection of the discontinuity.

14. The apparatus of claim 9 wherein the loop controller is further operative, after the detected discontinuity has passed, to gradually return the clock recovery loop from the particular state in which it was placed responsive to detection of the discontinuity to a normal operating state.

15. The apparatus of claim 14 wherein the loop controller in returning the clock recovery loop to the normal operating state applies a ramping function to the frequency error estimate such that the frequency error estimate is gradually reintroduced into the loop over a plurality of samples.

16. The apparatus of claim 9 wherein the discontinuity detector generates a signal given by:

17. The apparatus of claim 9 wherein the discontinuity detector generates a signal given by:

18. The apparatus of claim 1 wherein the sequence of arrival timestamps comprises a sequence of arrival timestamps generated for respective earliest-arrival ones of the timing messages with each such earliest-arrival timing message being selected, from a corresponding group of multiple timing messages received in the slave device from the master device, as the timing message of that group having the lowest network transit delay.

19. The apparatus of claim 18 wherein the network transit delay is determined for a given one of the timing messages as a difference between the arrival timestamp generated for the given timing message in the slave device and a corresponding departure timestamp generated in the master device and received by the slave device.

20. The apparatus of claim 1 wherein the clock recovery module further comprises at least one discontinuity detector configured to detect a discontinuity in delays of respective ones of the timing messages.

21. The apparatus of claim 20 wherein the discontinuity detector generates current and delayed estimates of a spread signal, the spread signal representing a difference between an output of an earliest-arrival packet filtering operation and a corresponding output of at least one additional packet filtering operation, and further wherein the discontinuity is detecting by processing a ratio of the current and delayed estimates of the spread signal.

22. The apparatus of claim 21 wherein the discontinuity detector generates the spread signal and its current estimate as follows:

s₁₂[n]=F{T₂[k]−

T₁[k]}[n]−

EAPF{T₂[k]−

T₁[k]}[n]

ŝ

₁₂[n]=(1−

α

_je)·

ŝ

₁₂[n−

1]+α

_je·

s₁₂[n]

where s₁₂[n] denotes the spread signal, ŝ

₁₂ [n] denotes the current estimate of the spread signal, ŝ

₁₂ [n−

1] denotes a previous estimate of the spread signal, EAPF{.} is an operator that denotes the earliest-arrival packet filtering operation, F{.} is an operator that denotes the additional packet filtering operation, α

_je is a filter parameter, T₁[k] and T₂[k] are respective departure and arrival timestamps, k denotes an index of all arriving packets and n denotes an index of a given pair of packets identified by the respective EAPF{.} and F{.} operators.

23. The apparatus of claim 22 wherein the operator F{.} that denotes the additional packet filtering operation further comprises one of a latest-arrival packet filtering operator given by LAPF{T₂[k]−

T₁[k]}[n], a mean filtering operator given by mean{.}, and a median filtering operator given by median{.}.

24. The apparatus of claim 22 wherein the discontinuity detector generates a signal given by:

25. The apparatus of claim 22 wherein the discontinuity detector generates a signal given by:

26. The apparatus of claim 17 wherein the discontinuity detector generates a signal given by:

27. The apparatus of claim 1 wherein the communication device comprises a processor coupled to a memory, and the clock recovery module is implemented at least in part in software code that is stored in the memory and executed by the processor.

28. A method for use in a communication device, the communication device being operative as a slave device relative to another communication device that is operative as a master device, the method comprising the steps of:

receiving timing messages from the master device;

generating arrival timestamps for respective ones of the timing messages;

generating an estimate of error between a master clock frequency of the master device and a slave clock frequency of the slave device; and

controlling the slave clock frequency based on the error estimate to synchronize the slave clock frequency with the master clock frequency;

wherein the generating step comprises generating the error estimate as a maximum-likelihood estimate using slope fitting based on the arrival timestamps; and

wherein the controlling step comprises filtering the error estimate using a series combination of an adaptive-bandwidth filter and a proportional-integral controller.

29. A processor-readable storage medium having embodied therein executable program code that when executed by a processor of the communication device implements the steps of the method of claim 28.

30. A communication system, comprising:

at least first and second communication devices configured to communicate with one another over a packet network;

a first one of the communication devices being operative as a slave device relative to another one of the communication devices operative as a master device;

the first communication device comprising a clock recovery module;

the clock recovery module comprising a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device;

the clock recovery loop comprising;

a frequency error estimator configured to generate an estimate of error between the master clock frequency and the slave clock frequency; and

a loop filter;

wherein the frequency error estimator comprises a maximum-likelihood estimator with slope fitting based on a sequence of arrival timestamps generated in the slave device for respective timing messages received from the master device; and

wherein the loop filter comprises a series combination of an adaptive-bandwidth filter and a proportional-integral controller.