Device fabrication
First Claim
1. A method for device fabrication, comprising:
- providing a base wafer at a first fabrication facility as part of a front-end-of-the-line (FEOL) circuitry fabrication process;
forming active circuitry on a plurality of FEOL circuitry die on the base wafer, the FEOL circuitry fabrication process operative to configure each FEOL circuitry die for subsequent electrical coupling with one or more memory layers to be fabricated directly above each FEOL circuitry die;
transferring the base wafer from the first fabrication facility to a second fabrication facility as part of a back-end-of-the-line (BEOL) memory fabrication process; and
forming one or more layers of memory directly on top of each FEOL circuitry die using the BEOL memory fabrication process, the forming including electrically coupling a portion of the active circuitry in each FEOL circuitry die with the one or more layers of memory that are formed directly above each FEOL circuitry die.
3 Assignments
0 Petitions
Accused Products
Abstract
Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.
137 Citations
28 Claims
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1. A method for device fabrication, comprising:
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providing a base wafer at a first fabrication facility as part of a front-end-of-the-line (FEOL) circuitry fabrication process; forming active circuitry on a plurality of FEOL circuitry die on the base wafer, the FEOL circuitry fabrication process operative to configure each FEOL circuitry die for subsequent electrical coupling with one or more memory layers to be fabricated directly above each FEOL circuitry die; transferring the base wafer from the first fabrication facility to a second fabrication facility as part of a back-end-of-the-line (BEOL) memory fabrication process; and forming one or more layers of memory directly on top of each FEOL circuitry die using the BEOL memory fabrication process, the forming including electrically coupling a portion of the active circuitry in each FEOL circuitry die with the one or more layers of memory that are formed directly above each FEOL circuitry die. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for device fabrication, comprising:
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forming a first part of an integrated circuit (IC) at a first fabrication facility, the IC initially comprises a front-end-of-the-line (FEOL) circuitry die formed on a base wafer using a FEOL circuitry fabrication process; and forming a second part of the IC at a second fabrication facility, the second part comprises one or more layers of memory that are directly fabricated above each FEOL circuitry die using a back-end-of-the-line (BEOL) memory fabrication process, wherein after the forming of the first part and the second part, the IC comprises a unitary die including a base layer with active circuitry fabricated thereon and one or more memory layers in contact with and positioned above the base layer and electrically coupled with at least a portion of the active circuitry. - View Dependent Claims (13, 14, 15, 16)
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17. A method for device fabrication, comprising:
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providing a trailing edge front-end-of-the-line (FEOL) circuitry fabrication technology configured for fabricating FEOL circuitry die on a base wafer at a first investment cost using capital assets that are substantially depreciated and selected for fabricating the FEOL circuitry die at a first cost per wafer; and providing a leading edge back-end-of-the-line (BEOL) memory fabrication technology configured for fabricating one or more BEOL memory layers directly on top of each FEOL circuitry die on the base wafer at a second investment cost that is greater than the first investment cost using capital assets having substantially no depreciation and selected for fabricating the one or more BEOL memory layers at a second cost per wafer that is greater than the first cost per wafer. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification