MASK PATTERN CORRECTING METHOD, MASK PATTERN INSPECTING METHOD, PHOTO MASK MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

• US 20100159709A1
• Filed: 03/04/2010
• Published: 06/24/2010
• Est. Priority Date: 03/02/2004
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KOTANI, Toshiya, Inoue, Soichi, Hashimoto, Koji, Nojima, Shigeki, Tanaka, Satoshi
• Granted Patent: US 8,142,961 B2
• Time in Patent Office: Days
• US Class Current: 438/735
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.

Claims

1-14. -14. (canceled)

15. A pattern correcting method for correcting design patterns to form a desired pattern on a wafer, the method comprising:

preparing a circuit model;

defining an allowable dimensional change quantity for the circuit model;

assigning the allowable dimensional change quantity to each of a plurality of design patterns included in a design layout;

calculating a dimension of a finished pattern of said each design pattern on a wafer;

acquiring a difference between the dimension of the finished pattern and a dimension of a desired pattern of said each design pattern on the wafer;

checking whether or not the difference of the dimensions satisfies the allowable dimensional change quantity for said each design pattern; and

correcting said each design pattern so that the difference of the dimensions satisfies the allowable dimensional change quantity.

16. A pattern correcting method according to claim 15, wherein the each design pattern is a gate pattern or a wiring pattern.

17. A pattern correcting method according to claim 15, wherein the allowable dimensional change quantity is defined based on at least one of a width of said each design pattern, a width of a space adjacent to said each design pattern, and a length of an extension portion of said each design pattern from an element region.

18. A pattern correcting method according to claim 15, wherein the allowable dimensional change quantity is different between a corner portion of said each design pattern and a portion other than the corner portion of said each design pattern.

19. A pattern correcting method according to claim 15, wherein correcting said each design pattern comprises:

defining a pattern correction condition for said each design pattern based on the allowable dimensional change quantity;

carrying out a simulation of an operation using the circuit model; and

determining, based on the simulation, whether or not a predetermined operation margin is attained for the circuit model, and performing correction for said each design pattern based on the pattern correction condition until it is determined that the predetermined operation margin is attained.

20. A pattern correcting method according to claim 19, wherein performing correction for said each design pattern comprises carrying out the simulation of the operation using the circuit model, determining whether or not the predetermined operation margin is attained as a result of the simulation, and performing further correction based on the pattern correction condition until it is determined that the predetermined operation margin is attained.

21. A pattern correcting method according to claim 19, wherein performing correction for said each design pattern is carried out so that, based on the pattern correction condition defined for said each design pattern, the difference of the dimensions satisfies the allowable dimensional change quantity.

22. A mask manufacturing method for manufacturing a mask for lithography by using pattern data of a design pattern corrected by the pattern correcting method claimed in claim 15.

23. A semiconductor device manufacturing method for manufacturing a semiconductor device by using a mask for lithography manufactured by the mask manufacturing method claimed in claim 22.

24. A pattern inspecting method for inspecting a design pattern corrected by the pattern correcting method according to claim 15, the pattern inspecting method comprising:

defining a pattern inspection condition for said each design pattern after being corrected, based on the allowable dimensional change quantity, and

inspecting said each design pattern based on the pattern inspection condition defined for said each corrected design pattern.

25. A pattern inspecting method according to claim 24, wherein inspecting said each design pattern comprises inspecting, based on the pattern correction condition defined for said each design pattern, whether or not the difference of the dimensions satisfies the allowable dimensional change quantity.

26. A mask manufacturing method for manufacturing a mask for lithography by using pattern data of a design pattern inspected by the pattern inspecting method claimed in claim 24.

27. A semiconductor device manufacturing method for manufacturing a semiconductor device by using a mask for lithography manufactured by the mask manufacturing method claimed in claim 26.

28. A pattern correcting method according to claim 15, wherein said design patterns to which the allowable dimensional change quantity are assigned are design patterns of patterns to be formed on different layers on the wafer.

29. A pattern correcting method according to claim 19, wherein the pattern data correction condition include at least one conditional element of a correction convergence condition for determining whether or not to terminate correction in accordance with the difference of the dimensions after correction, a minimum unit area of a correction region of the design pattern, a maximum move quantity allowable for the design pattern, a minimum width of the design pattern, and a minimum space width adjacent to the design pattern.

31. A pattern inspecting program executable by a computer, for inspecting a design pattern corrected by the pattern correcting method according to claim 15, the pattern inspecting program comprising:

defining a pattern inspection condition for said each design pattern after being corrected, based on the allowable dimensional change quantity, and

inspecting said each design pattern based on the pattern inspection condition defined for said each corrected design pattern.

30. A pattern correcting program executable by a computer, for correcting design patterns to form a desired pattern on a wafer, the program comprising:

preparing a circuit model;

defining an allowable dimensional change quantity for the circuit model;

assigning the allowable dimensional change quantity to each of a plurality of design patterns included in a design layout;

checking a difference of a dimensional change quantity of said each design pattern from the allowable dimensional change quantity; and

correcting the difference of the dimensional change quantity of said each design pattern from the allowable dimensional change quantity.