IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE

• US 20100159785A1
• Filed: 01/05/2010
• Published: 06/24/2010
• Est. Priority Date: 12/30/2003
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lee, Dong Hoon, Lee, Jae Kyun
• Granted Patent: US 8,670,083 B2
• Time in Patent Office: Days
• US Class Current: 445/24
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G09G 2300/0434 Flat panel display in which a field is applied parallel to the display plane
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

Abstract

An IPS mode LCD device is disclosed in which a common voltage drop and delay is decreased. The LCD includes gate and data lines crossing each other to define pixel regions. Thin film transistors are formed at crossing portions of the gate and data lines. Common lines are parallel with the gate lines and common electrodes project from the common lines parallel with the data lines. Pixel electrodes connected with drain electrodes of the thin film transistors are formed in the pixel regions between the parallel common electrodes. A first common voltage supplying line applies a first common voltage or a second common voltage to a closed circuit formed by grouping the adjacent odd numbered common lines. A second common voltage supplying line applies the second common voltage or the first common voltage to a closed circuit formed by grouping the adjacent even numbered common lines.

Claims

1. A method comprising:

forming gate lines, first and second common lines parallel with the gate lines, and common electrodes projecting from the first and second common lines in the same layer;

covering the gate lines, the first and second common lines and the common electrodes with an insulating layer;

forming first and second contact holes in the insulating layer;

forming data lines and first and second common voltage supplying lines in the same layer on the insulating layer, wherein the data lines cross the gate lines and define pixel regions and wherein the first common voltage supplying lines are connected with the first common lines through the first contact holes and the second common voltage supplying lines are connected with the second common lines through the second contact holes;

coating a passivation layer on the data lines and the first and second common voltage supplying lines;

forming pixel electrodes on the passivation layer, the pixel electrodes between the common electrodes in the pixel regions,

wherein the first and second common lines alternate in a direction along the data lines,

wherein the first and second contact holes are formed at an outer region of a display region including the pixel regions and are not formed in the display region,

wherein the first common voltage supplying lines are directly connected with both ends of the respective first common lines through the first contact holes at the outer region so that form a first closed circuit by grouping the first common lines,

wherein the second common voltage supplying lines are directly connected with both ends of the respective second common lines through the first contact holes so that form a second closed circuit by grouping the second common lines.