FLASH INITIATIVE WEAR LEVELING ALGORITHM

• US 20100161880A1
• Filed: 12/27/2006
• Published: 06/24/2010
• Est. Priority Date: 12/27/2006
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: You, Guangqing
• Granted Patent: US 8,356,152 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A method and apparatus for initiative wear leveling for non-volatile memory. An embodiment of a method includes counting erase cycles for each of a set of multiple memory blocks of a non-volatile memory, the counting of erase cycles for each memory block including incrementing a first count for a physical block address of the memory block, and if the memory block is not a spare memory block, incrementing a second count for a logical block address of the memory block. The method also includes determining whether the non-volatile memory has uneven wear of memory blocks based at least in part on the counting of the erase cycles of the plurality of memory blocks.

Claims

1. A method comprising:

counting erase cycles for each of a plurality of memory blocks of a non-volatile memory, the counting of erase cycles for each memory block including;

incrementing a first count for a physical block address of the memory block, and

if the memory block is not a spare memory block, incrementing a second count for a logical block address of the memory block; and

determining whether the non-volatile memory has uneven wear of memory blocks based at least in part on the counting of the erase cycles of the plurality of memory blocks.

2. The method of claim 1, wherein if the non-volatile memory has uneven wear, then:

identifying a first group of memory blocks of the non-volatile memory having high levels of wear and a second group of memory blocks of the non-volatile memory having low levels of wear, and

exchanging data from one or more memory blocks of the first group with data from one or more memory blocks of the second group.

3. The method of claim 2, wherein exchanging data between a first memory block and a second memory block of the plurality of memory blocks includes transferring the logical block address from the first memory block to the second memory block.

4. The method of claim 2, wherein exchanging data from one or more memory blocks of the first group with data from one or more memory blocks of the second group includes a series of memory block reclaim operations.

5. The method of claim 1, wherein determining whether the non-volatile memory has uneven we of memory blocks comprises generating a line by linear regression to represent the erase cycles for each physical block address and the erase cycles for each logical block address.

6. The method of claim 1, wherein determining whether the non-volatile memory has uneven wear of memory blocks further comprises comparing a slope of the generated line to a slope threshold.

7. The method of claim 6, wherein the slope of the generated line is compared with the slope threshold after a predetermined number of erase cycles for the non-volatile memory have occurred.

8. The method of claim 1, wherein the non-volatile memory is a flash memory.

9. A non-volatile memory device comprising:

a memory array, the memory array including a plurality of memory blocks, each memory block having a physical block address. and each memory block either having a logical block address or being a spare block;

a memory controller coupled with the memory array, the memory controller to control the storage of data in the memory array; and

one or ore registers to record the number of erase operations for the plurality of memory blocks of the memory array, the one or more registers including a count of erase cycles for each physical block address and a count of erase cycles for each logical block address.

10. The device of claim 9, wherein the memory controller is to determine the slope of a line representing the number of erase cycles for each physical block address and the number of erase cycles for each logical block address.

11. The device of claim 10, wherein the memory controller determines the slope of the line after a predetermined number of erase cycles has occurred.

12. The device of claim 10, wherein the memory controller is to compare the slope of the line with a threshold value, the memory controller to perform a switch of memory blocks if the slope of the line exceeds the threshold.

13. The device of claim 12, wherein the switch of memory blocks includes switching data between a first group of the memory blocks having high erase counts with a second group of memory blocks having low erase counts.

14. The device of claim 9, wherein the memory array comprises a flash memory array.

15. A computer system comprising:

a bus;

a flash memory device coupled with the bus, the non-volatile memory device including a plurality of memory blocks;

a dynamic random access memory coupled with the bus; and

a processor coupled with the bus, the processor to transfer data between the dynamic random access memory and the flash memory device;

wherein the system tracks the number of erase cycles for each of the memory blocks by physical block address and by logical block address.

16. The system of claim 15, wherein the system is to determine whether the flash memory device has uneven wear based at least in part on the number of erase cycles for each of the memory blocks by physical block address and by logical block address.

17. The system of claim 16, wherein the system is to determine whether the flash memory device has uneven wear by comparing the slope of a regression line for the number of erase cycles for each of the memory blocks by physical block address and by logical block address with a slope threshold.

18. The system of claim 16, wherein the system is to determine whether the flash memory device has uneven wear each time a predetermined number of erase cycles has occurred.

19. A computer-readable medium having stored thereon data representing sequences of instructions that, when executed by a processor. cause the processor to perform operations comprising:

counting erase cycles for each of a plurality of memory blocks of a flash memory, the counting of erase cycles for a memory block including;

incrementing a first count for a physical block address of the memory block, and

if the memory block is not a spare memory block. incrementing a second count for a logical block address of the memory block; and

determining whether the flash memory has uneven wear of memory blocks based at least in part on the counting of the erase cycles of the plurality of memory blocks.

20. The medium of claim 19, further comprising instructions that, when executed by a processor, cause the processor to perform operations comprising:

identifying a first group of memory blocks of the flash memory having high levels of wear and a second group of memory blocks of the non-volatile memory having low levels of wear, and

exchanging data from one or more memory blocks of the first group with data from one or more memory blocks of the second group.

21. The medium of claim 20, wherein exchanging data from one or more memory blocks of the first group with data from one or more memory blocks of the second group includes a series of memory block reclaim operations.

22. The medium of claim 19, wherein determining whether the flash memory has uneven wear of memory blocks comprises generating a line by linear regression to represent the erase cycles for each physical block address and the erase cycles for each logical block address, and comparing a slope of the generated line to a slope threshold.