Architecture for Address Mapping of Managed Non-Volatile Memory

• US 20100161886A1
• Filed: 11/06/2009
• Published: 06/24/2010
• Est. Priority Date: 12/23/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Herman, Kenneth L., Toelkes, Tahoma, Khmelnitsky, Vadim, Post, Daniel Jeffrey, Wakrat, Nir Jacob, Corlett, Barry, Fai, Anthony, Thio, Hsiao
• Granted Patent: US 8,370,603 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

Claims

1. A non-volatile memory (NVM) package, comprising:

an interface operable for receiving a block address;

a plurality of concurrent access units each containing a plurality of blocks; and

a processor coupled to the interface and the plurality of concurrently addressable units, the processor operable for mapping the block address to a block in one of the plurality of concurrently addressable units identified by the block address.

2. The package of claim 1, further comprising:

a host interface operable for receiving a host chip enable signal from a host processor coupled to the host interface, where the processor is operable for mapping the host chip enable signal to a chip enable signal internal to one of the concurrently addressable units, the internal chip enable signal for activating the concurrently addressable unit.

3. The package of claim 2, where the mapping is performed using a map defined by run and stride parameters, where the run parameter is the number of concurrently addressable units that are accessible using the host chip enable signal, and the stride parameter is the number of blocks for an operation command within a concurrently addressable unit.

4. The package of claim 1, where the processor receives a command from the interface for a read or write operation, the operation being a sequence of read or write commands that perform concurrent atomic transactions on one or more concurrently addressable units.

5. The package of claim 4, where a quantity of data that is read from, or written to the concurrently addressable unit, is equal to a product of N, a stride parameter for the concurrently addressable unit and a number of bytes equivalent to a page size plus a number of bytes associated with page allowing for metadata, where N is a positive integer representing a number of pages to be read or written, and stride is a number of blocks for operation commands within the concurrently addressable unit.

6. The package of claim 1, further comprising:

an error correction engine for applying error correction to a block of date read from, or written to a concurrently addressable unit.

7. The package of claim 6, where the error detection and correction engine is included in one or more of the concurrently addressable units.

8. The package of claim 1, further comprising:

a pipeline management engine for managing throughput to the concurrently addressable units.

9. The package of claim 1, where the NVM package is managed NAND.

10. The package of claim 1, where the processor performs concurrent read or write operations on two or more concurrently addressable units.

11. A method performed by non-volatile memory (NVM) package coupled to a host processor, comprising:

receiving a block address from the host processor; and

mapping the block address to a block in one of a plurality of concurrently addressable units identified by the block address.

12. The method of claim 11, further comprising:

receiving a host chip enable signal from the host processor; and

mapping the host chip enable signal to a chip enable signal internal to one of the concurrently addressable units; and

activating the internal chip enable signal.

13. The method of claim 12, where the mapping is performed using a map defined by run and stride parameters, where the run parameter is the number of concurrently addressable units that are accessible using the host chip enable signal, and the stride parameter is the number of blocks for an operation command within a concurrently addressable unit.

14. The method of claim 11, further comprising:

receiving a command for a read or write operation; and

performing one or more concurrent atomic transactions on one or more concurrently addressable units according to the command.

15. The method of claim 14, where a quantity of data that is read from, or written to the concurrently addressable unit, is equal to a product of N, a stride parameter for the concurrently addressable unit and a number of bytes equivalent to a page size plus a number of bytes associated with page allowing for metadata, where N is a positive integer representing a number of pages to be read or written, and stride is a number of blocks for operation commands within the concurrently addressable unit.

16. The package of claim 11, further comprising:

applying error correction to a block of data read from, or written to a concurrently addressable unit.

17. A non-volatile memory (NVM) package, comprising:

an interface operable for receiving a block address and a first chip enable signal from a host processor coupled to the interface;

a plurality of concurrent access units each containing a plurality of blocks; and

a processor coupled to the interface and the plurality of concurrently addressable units, where in response to the chip enable signal from the host processor, the processor activates a first concurrently addressable unit using a first internal chip select enable signal, activating a second concurrently addressable unit using a second, internal chip select enable signal, mapping the block address to blocks in the activated first and second concurrently addressable units, and executing a sequence of commands for concurrently performing read or write operations on the blocks in the activated first and second currently addressable units.

18. The package of claim 17, where the NVM package is a managed NAND package.

19. A system that operates on data stored in a non-volatile memory (NVM) package, comprising:

an interface for sending a request for parameters to the NVM package, the NVM package including a plurality of concurrently addressable units, and for receiving a run parameter and a stride parameter, where the run parameter indicates a number of concurrently addressable units in the NVM package that are accessible using a single chip enable signal provided by the host processor, and where the stride parameter indicates a number of blocks for an operation command within a concurrently addressable unit; and

a processor coupled to the interface, the processor operable for sending a sequence of commands to the NVM package for concurrently performing atomic transactions on one or more concurrently addressable units, the sequence of commands including an address generated by the host processor based on the run and stride parameters.

20. The system of claim 19, wherein the processor is operable to send data with a write command to the NVM package, where the data size is equal to the product of N, the stride, and a number of bytes equivalent to a page size plus a number of bytes associated with each page size allowing for metadata, where N is a positive integer representing a number of pages to be written.

21. The system of claim 19, where the processor is operable to send a read command to the NVM package, where the data size to be read is equal to the product of N, the stride, and a number of bytes equivalent to a page size plus a number of bytes associated with each page size allowing for metadata, where N is a positive integer representing a number of pages to be read.

22. A method performed by host processor coupled to a non-volatile memory (NVM) package, comprising:

sending a request for parameters to the NVM package, the NVM package including a plurality of concurrently addressable units;

responsive to the request, receiving a run parameter and a stride parameter, where the run parameter indicates a number of concurrently addressable units in the NVM package that are accessible using a single chip enable signal provided by the host processor, and where the stride parameter indicates a number of blocks for an operation command within a concurrently addressable unit; and

sending a sequence of commands to the NVM package for concurrently performing atomic transactions on one or more concurrently addressable units, the sequence of commands include an address generated by the host processor based on the run and stride parameters.

23. The method of claim 22, further comprising:

sending data with a write command to the NVM package, where the data size is equal to the product of N, the stride, and a number of bytes equivalent to a page size plus a number of bytes associated with each page size allowing for metadata, where N is a positive integer representing a number of pages to be written.

24. The method of claim 22, further comprising:

sending a read command to the NVM package, where the data size to be read is equal to the product of N, the stride, and a number of bytes equivalent to a page size plus a number of bytes associated with each page size allowing for metadata, where N is a positive integer representing a number of pages to be read.

25. A method performed by an embedded non-volatile memory device, comprising:

receiving commands from a host controller requesting operations on non-volatile memory;

storing the commands in a queue of the non-volatile memory device; and

reordering the commands in the queue in response to a trigger event.

26. A method performed by en embedded non-volatile memory device, comprising:

receiving read commands from a host controller requesting read operations on non-volatile memory;

storing the read commands in a first queue;

receiving program commands from the host controller requesting program operations on the non-volatile memory;

storing the program commands in a second queue;

receiving erase commands from the host controller requesting erase operations on the non-volatile memory

storing the erase commands in a third queue; and

reordering one or more of the read, program or erase commands in their respective queues.