Data storage system with non-volatile memory using both page write and block program and block erase

• US 20100161888A1
• Filed: 12/18/2009
• Published: 06/24/2010
• Est. Priority Date: 12/22/2008
• Status: Abandoned Application

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Eggleston, David
• Application Number:
  US12/653,938
• Publication Number:
  US 20100161888A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

An optimized data storage system including non-volatile re-writeable memory having both block program and erase and full or partial page write is disclosed. A memory controller of the system can use block data operations for large data transfers, and page data operations for small data transfers. Page data operations in the non-volatile re-writeable memory do not require block rewrites. One or more layers of the non-volatile re-writeable memory can be fabricated BEOL as two-terminal cross-point memory arrays that are fabricated over a substrate including active circuitry fabricated FEOL. Some or all of the active circuitry can be electrically coupled with the one or more layers of two-terminal cross-point memory arrays to perform data operations on the arrays, such as the block program and block erase and/or full or partial page writes. The arrays can include a plurality of two-terminal memory cells.

Claims

1. A data storage system, comprising:

at least one non-volatile memory that does not require an erase operation on the at least one non-volatile memory prior to a write operation on the at least one non-volatile memory; and

access circuitry electrically coupled with a memory interface and the at least one non-volatile memory, the memory interface operative to electrically communicate signals for data operations on the at least one non-volatile memory with the access circuitry, and the access circuitry operative to perform the data operations on the at least one non-volatile memory, and

wherein the signals include one or more commands for data operations configured to operate on at least one page address within a block of data stored in the at least one non-volatile memory.

2. The data storage system of claim 1, wherein the at least one non-volatile memory comprises at least one back-end-of-the-line (BEOL) non-volatile memory and the access circuitry comprises front-end-of-the-line (FEOL) access circuitry positioned on a substrate that the at least one BEOL non-volatile memory is in contact with and is fabricated directly above.

3. The data storage system of claim 1, wherein the at least one non-volatile memory includes a plurality of two-terminal non-volatile memory cells operative to store at least one-bit of data as a plurality of conductivity profiles.

4. The data storage system of claim 1, wherein the one or more commands for data operations comprises a full page write.

5. The data storage system of claim 1, wherein the one or more commands for data operations comprises a partial page write.

6. The data storage system of claim 1, wherein the one or more commands for data operations comprises a full page program after a page erase.

7. The data storage system of claim 1, wherein the one or more commands for data operations comprises a partial page program after a page erase.

8. The data storage system of claim 1, wherein the one or more commands for data operations comprises a partial page program after a partial page erase.

9. The data storage system of claim 1, wherein the one or more commands for data operations comprises commands configured for data operations on FLASH memory and include an erase operation prior to a write operation.

10. The data storage system of claim 9, wherein the erase operation is a block erase on a block of data in the at least one non-volatile memory.

11. The data storage system of claim 9, wherein the write operation comprises a page program operation.

12. The data storage system of claim 9, wherein the erase operation on the at least one non-volatile memory is mimicked and does not occur, and wherein signals consistent with the erase operation having been consummated are generated by the access circuitry and communicated over the memory interface.

13. The data storage system of claim 1, wherein the at least one non-volatile memory comprises a component in a solid state drive (SSD).

14. The data storage system of claim 1, wherein the at least one non-volatile memory comprises a component in an embedded storage device.

15. A data storage system, comprising:

a controller electrically coupled with a host interface and a memory interface, the host interface operative to electrically communicate data operation signals between the controller and an external host system, and the controller operative to electrically communicate the data operation signals with the memory interface;

at least one non-volatile memory that does not require an erase operation on the at least one non-volatile memory prior to a write operation on the at least one non-volatile memory; and

access circuitry electrically coupled with the memory interface and the at least one non-volatile memory, the memory interface operative to electrically communicate the data operation signals from the controller to access circuitry, and the access circuitry operative to perform data operations on the at least one non-volatile memory based on the data operation signals, and

wherein the data operation signals include one or more commands for data operations configured to operate on at least one page address within a block of data stored in the at least one non-volatile memory.

16. The data storage system of claim 15, wherein the controller includes a processor, a command decoder electrically coupled with the processor and operative to decode commands communicated over the host interface, and a DMA sequencer electrically coupled with the processor.

17. The data storage system of claim 15, wherein the at least one non-volatile memory comprises at least one back-end-of-the-line (BEOL) non-volatile memory and the access circuitry comprises front-end-of-the-line (FEOL) access circuitry positioned on a substrate that the at least one BEOL non-volatile memory is in contact with and is fabricated directly above.

18. The data storage system of claim 15, wherein the one or more commands for data operations comprises a full page write.

19. The data storage system of claim 15, wherein the one or more commands for data operations comprises a partial page write.

20. The data storage system of claim 15, wherein the one or more commands for data operations comprises a full page program after a page erase.

21. The data storage system of claim 15, wherein the one or more commands for data operations comprises a partial page program after a page erase.

22. The data storage system of claim 15, wherein the one or more commands for data operations comprises a partial page program after a partial page erase.

23. A data storage system, comprising:

at least one non-volatile memory that requires an erase operation on the at least one non-volatile memory prior to a write operation on the at least one non-volatile memory; and

access circuitry electrically coupled with a memory interface and the at least one non-volatile memory, the memory interface operative to electrically communicate signals for data operations on the at least one non-volatile memory with the access circuitry, and the access circuitry operative to perform the data operations on the at least one non-volatile memory, and

wherein the signals include one or more commands for data operations configured to operate on at least one page address within a block of data stored in the at least one non-volatile memory.

24. A data storage system, comprising:

a controller electrically coupled with a host interface and a memory interface, the host interface operative to electrically communicate data operation signals between the controller and an external host system, and the controller operative to electrically communicate the data operation signals with the memory interface;

at least one non-volatile memory that requires an erase operation on the at least one non-volatile memory prior to a write operation on the at least one non-volatile memory; and

access circuitry electrically coupled with the memory interface and the at least one non-volatile memory, the memory interface operative to electrically communicate the data operation signals from the controller to access circuitry, and the access circuitry operative to perform data operations on the at least one non-volatile memory based on the data operation signals, and

wherein the data operation signals include one or more commands for data operations configured to operate on at least one page address within a block of data stored in the at least one non-volatile memory.